2.2 BSP Rel. 1.0 for PPMC-275 Programmer's Guide

List of APIs API Call Reference
Table 14:MPSC Main Structure: MPSC_MAIN_STRUCT (cont.)
Bits Field Bit
Width
22 RDW 1 Receive Data Width
0 - Normal mode. The MPSC data path
is 16 bits wide. Upon receiving 16 bits,
the data is transferred into the SDMA
FIFOs. Buffers must be 64-bit word
aligned. DMA bursts are enabled.
21 reserved1 1
Description
Note:
• Normal Mode must be used
for HDLC based protocols. 1
- Low latency operation.
Data is transferred to the
FIFOs after 8 bits are
received. Logical FIFO
width is one byte.
• This mode allows byte
aligned buffers. This mode
must be chosen for BISYNC
and UART modes. DMA
bursts are disabled. The
SDMA writes one byte per
DRAM access. Setting RDW
also bypasses the receive
FIFO threshold. The SDMA
arbitrates for DMA access as
soon as the FIFO has one
byte in it.
20:17 GDW 4 Clock Glitch Width
When the GDE bit is set, the MPSC will
consider Tx/Rx clock pulses that are
narrower than GDW system clocks as a
glitch.
5 - 78 VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275