2.2 BSP Rel. 1.0 for PPMC-275 Programmer's Guide

List of APIs API Call Reference
use the value of 0 by default for this parameter), Device number on
the bus, Function number within the device (will be combined
with the register offset) and Configuration register offset within
the device/function being accessed. A subsequent read to the PCI
Configuration Data register causes the GT to translate that Configuration
Address value to the requested cycle on the PCI bus (in
this case - read) or internal configuration space. This function
reads from an agent’s configuration register at any of the eight
possible function in its Configuration Space Header.
EXAMPLE The value 0x004 is combined from the function number (bits[11:8])
and the register offset (bits[7:0]) in the Configuration Space
Header. In this case, the fuction number is 0 and the register offset
is 0x04.
...
data = frcPci0ReadConfigReg(0x004,6);
...
The configuration address register (0xCF8) fields are:
INPUT
regOffset The register offset PCI configuration Space Header combined with
the function number as shown in the example above.
pciDevNum The agent’s device number.
OUTPUT PCI write configuration cycle.
RETURN 32 bit read data from the agent's configuration register. if the data
= 0xffffffff check the master abort bit in the cause register to make
sure the data is valid.
void frcPci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum, unsigned int
data)
DESCRIPTION The MV holds two registers to support configuration accesses as
defined in the PCI spec Rev 2.2: Configuration Address and
Configuration Data registers. The mechanism for accessing
configuration space is to write a value into the Configuration
Address register that specifies the PCI bus number (this function
5 - 22 VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275