Tutorial CUDA

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Host Runtime Component: Device Management Device enumeration cudaGetDeviceCount(), cudaGetDeviceProperties() Device selection cudaChooseDevice(), cudaSetDevice() © NVIDIA Corporation 2008
Host Runtime Component: Memory Management Two kinds of memory: © NVIDIA Corporation 2008 Linear memory: accessed through 32-bit pointers <strong>CUDA</strong> arrays: opaque layouts with dimensionality, only readable through texture fetching Device memory allocation cudaMalloc(), cudaMallocPitch(), cudaFree(), cudaMallocArray(), cudaFreeArray() Memory copy from host to device, device to host, device to device cudaMemcpy(), cudaMemcpy2D(), cudaMemcpyToArray(), cudaMemcpyFromArray(), etc. cudaMemcpyToSymbol(), cudaMemcpyFromSymbol() Memory addressing cudaGetSymbolAddress()
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Tutorial CUDA Cyril Zeller NVIDIA D
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© NVIDIA Corporation 2008 GPU Comp
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Parallel Computing’s Dark Age But
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Enter the GPU GPU = Graphics Proces
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Enter CUDA CUDA is a scalable paral
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110-240X © NVIDIA Corporation 2008
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GPUs Are Getting Faster, Faster ©
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© NVIDIA Corporation 2008 CUDA Pro
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Heterogeneous Programming CUDA = se
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Hierarchy of Concurrent Threads Thr
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Memory Hierarchy Sequential Kernels
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CUDA Language: C with Minimal Exten
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Example: Increment Array Elements C
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Example: Host Code // allocate host
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More on Memory Spaces Each thread c
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Compiling CUDA for NVIDIA GPUs Any
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Device Emulation Mode Pitfalls Emul
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Reduction Exercise At the end of ea
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Reduce 1: Blocking the Data Block I
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Reduce 1: Multi-Pass Reduction Bloc
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© NVIDIA Corporation 2008 CUDA Imp
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Hardware Implementation: A Set of S
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Hardware Implementation: Execution
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Host Synchronization All kernel lau
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Multiple CPU Threads and CUDA CUDA
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Performance Optimization Expose as
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Expose Parallelism: CPU/GPU Paralle
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Minimize CPU ↔ GPU Data Transfers
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Global Memory Reads/Writes Global m
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Coalesced Global Memory Accesses ©
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Non-Coalesced Global Memory Accesse
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Avoiding Non-Coalesced Accesses For
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Profiler Signals Events are tracked
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Back to Reduce Exercise: Profile wi
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Reduce 2 Thread IDs Block IDs Distr
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Maximize Use of Shared Memory Share
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Example: Square Matrix Multiplicati
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Example: Avoiding Non-Coalesced flo
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Execution Configuration: Constraint
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Execution Configuration: Heuristics
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Back to Reduce Exercise: Problem wi
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Parallel Reduction Complexity Takes
Page 89 and 90: Reduce 3: Go Ahead! Open up reduce\
Page 91 and 92: Arithmetic Instruction Throughput f
Page 93 and 94: Runtime Math Library There are two
Page 95 and 96: What You Need To Know FP64 instruct
Page 97 and 98: Mixed Precision Arithmetic Research
Page 99 and 100: Single Precision Floating Point ©
Page 101 and 102: Instruction Predication Comparison
Page 103 and 104: Shared Memory Is Banked Bandwidth o
Page 105 and 106: Bank Addressing Examples 2-way bank
Page 107 and 108: Back to Reduce Exercise: Problem wi
Page 109 and 110: Reduce 3: Bank Conflicts Showed for
Page 111 and 112: Reduce 4: Go Ahead! Open up reduce\
Page 113 and 114: Reduce 5: Unrolled Loop if (numThre
Page 115 and 116: Reduce 5: Final Unrolled Loop if (n
Page 117 and 118: Coming Up Soon CUDA 2.0 © NVIDIA C
Page 119 and 120: Extra Slides
Page 121 and 122: Applications - Condensed 3D image a
Page 123 and 124: Performance GPU Electromagnetic Fie
Page 125 and 126: EvolvedMachines 130X Speed up Brain
Page 127 and 128: nbody Astrophysics Astrophysics res
Page 129 and 130: A quick review device = GPU = set o
Page 131 and 132: Language Extensions: Function Type
Page 133 and 134: Language Extensions: Execution Conf
Page 135 and 136: Common Runtime Component Provides:
Page 137 and 138: Common Runtime Component: Mathemati
Page 139: Host Runtime Component Provides fun
Page 143 and 144: Host Runtime Component: Interoperab
Page 145 and 146: Host Runtime Component: Error Handl
Page 147 and 148: Device Runtime Component: Mathemati
Page 149 and 150: Device Runtime Component: Texture F
Page 151 and 152: Compilation Any source file contain
Page 153 and 154: Role of Open64 Open64 compiler give
Page 155 and 156: CUDA Libraries CUBLAS CUFFT © NVID
Page 157: CUFFT Library Efficient implementat
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