Tutorial CUDA

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Reduce 3: Parallel Reduction Implementation Step 1 Stride 1 Step 2 Stride 2 Step 3 Stride 4 Step 4 Stride 8 © NVIDIA Corporation 2008 Indices Values Thread IDs Values Thread IDs Values Thread IDs Values Thread IDs Values 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10 1 8 -1 0 -2 3 5 -2 -3 2 7 0 11 0 2 0 1 2 3 4 5 6 7 11 1 7 -1 -2 -2 8 5 -5 -3 9 7 11 11 2 2 0 1 2 3 18 1 7 -1 6 -2 8 5 4 -3 9 7 13 11 2 2 0 1 24 1 7 -1 6 -2 8 5 17 -3 9 7 13 11 2 2 0 41 1 7 -1 6 -2 8 5 17 -3 9 7 13 11 2 2
Parallel Reduction Complexity Takes log(N) steps and each step S performs N/2 S independent operations © NVIDIA Corporation 2008 Step complexity is O(log(N)) For N=2 D , performs ∑ S∈[1..D] 2 D-S = N-1 operations Work complexity is O(N) Is work-efficient (i.e. does not perform more operations than a sequential reduction) With P threads physically in parallel (P processors), performs ∑ S∈[1..D] ceil(2 D-S /P) operations ∑S∈[1..D]ceil(2D-S /P) < ∑S∈[1..D](floor(2D-S /P) + 1) < N/P + log(N) Time complexity is O(N/P + log(N)) Compare to O(N) for sequential reduction
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Tutorial CUDA Cyril Zeller NVIDIA D
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© NVIDIA Corporation 2008 GPU Comp
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Parallel Computing’s Dark Age But
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Enter the GPU GPU = Graphics Proces
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Enter CUDA CUDA is a scalable paral
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110-240X © NVIDIA Corporation 2008
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GPUs Are Getting Faster, Faster ©
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© NVIDIA Corporation 2008 CUDA Pro
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Heterogeneous Programming CUDA = se
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Hierarchy of Concurrent Threads Thr
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Memory Hierarchy Sequential Kernels
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CUDA Language: C with Minimal Exten
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Example: Increment Array Elements C
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Example: Host Code // allocate host
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More on Memory Spaces Each thread c
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Compiling CUDA for NVIDIA GPUs Any
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Device Emulation Mode Pitfalls Emul
Page 35 and 36: Reduction Exercise At the end of ea
Page 37 and 38: Reduce 1: Blocking the Data Block I
Page 39 and 40: Reduce 1: Multi-Pass Reduction Bloc
Page 41 and 42: © NVIDIA Corporation 2008 CUDA Imp
Page 43 and 44: Hardware Implementation: A Set of S
Page 45 and 46: Hardware Implementation: Execution
Page 47 and 48: Host Synchronization All kernel lau
Page 49 and 50: Multiple CPU Threads and CUDA CUDA
Page 51 and 52: Performance Optimization Expose as
Page 53 and 54: Expose Parallelism: CPU/GPU Paralle
Page 55 and 56: Minimize CPU ↔ GPU Data Transfers
Page 57 and 58: Global Memory Reads/Writes Global m
Page 59 and 60: Coalesced Global Memory Accesses ©
Page 61 and 62: Non-Coalesced Global Memory Accesse
Page 63 and 64: Avoiding Non-Coalesced Accesses For
Page 65 and 66: Profiler Signals Events are tracked
Page 67 and 68: Back to Reduce Exercise: Profile wi
Page 69 and 70: Reduce 2 Thread IDs Block IDs Distr
Page 71 and 72: Maximize Use of Shared Memory Share
Page 73 and 74: Example: Square Matrix Multiplicati
Page 75 and 76: Example: Avoiding Non-Coalesced flo
Page 81 and 82: Execution Configuration: Constraint
Page 83 and 84: Execution Configuration: Heuristics
Page 85: Back to Reduce Exercise: Problem wi
Page 89 and 90: Reduce 3: Go Ahead! Open up reduce\
Page 91 and 92: Arithmetic Instruction Throughput f
Page 93 and 94: Runtime Math Library There are two
Page 95 and 96: What You Need To Know FP64 instruct
Page 97 and 98: Mixed Precision Arithmetic Research
Page 99 and 100: Single Precision Floating Point ©
Page 101 and 102: Instruction Predication Comparison
Page 103 and 104: Shared Memory Is Banked Bandwidth o
Page 105 and 106: Bank Addressing Examples 2-way bank
Page 107 and 108: Back to Reduce Exercise: Problem wi
Page 109 and 110: Reduce 3: Bank Conflicts Showed for
Page 111 and 112: Reduce 4: Go Ahead! Open up reduce\
Page 113 and 114: Reduce 5: Unrolled Loop if (numThre
Page 115 and 116: Reduce 5: Final Unrolled Loop if (n
Page 117 and 118: Coming Up Soon CUDA 2.0 © NVIDIA C
Page 119 and 120: Extra Slides
Page 121 and 122: Applications - Condensed 3D image a
Page 123 and 124: Performance GPU Electromagnetic Fie
Page 125 and 126: EvolvedMachines 130X Speed up Brain
Page 127 and 128: nbody Astrophysics Astrophysics res
Page 129 and 130: A quick review device = GPU = set o
Page 131 and 132: Language Extensions: Function Type
Page 133 and 134: Language Extensions: Execution Conf
Page 135 and 136: Common Runtime Component Provides:
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Common Runtime Component: Mathemati
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Host Runtime Component Provides fun
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Host Runtime Component: Memory Mana
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Host Runtime Component: Interoperab
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Host Runtime Component: Error Handl
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Device Runtime Component: Mathemati
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Device Runtime Component: Texture F
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Compilation Any source file contain
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Role of Open64 Open64 compiler give
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CUDA Libraries CUBLAS CUFFT © NVID
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CUFFT Library Efficient implementat
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