Tutorial CUDA

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Step 2 Step 1 Example: Avoiding Non-Coalesced float3 Memory Accesses t0 t1 t2 © NVIDIA Corporation 2008 … GMEM SMEM t255 t0 t1 … … SMEM Similarly, Step3 starting at offset 512 t2 … …
Example: Avoiding Non-Coalesced float3 Memory Accesses Use shared memory to allow coalescing © NVIDIA Corporation 2008 Need sizeof(float3)*(threads/block) bytes of SMEM Each thread reads 3 scalar floats: Offsets: 0, (threads/block), 2*(threads/block) These will likely be processed by other threads, so sync Processing Each thread retrieves its float3 from SMEM array Cast the SMEM pointer to (float3*) Use thread ID as index Rest of the compute code does not change!
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Tutorial CUDA Cyril Zeller NVIDIA D
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© NVIDIA Corporation 2008 GPU Comp
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Parallel Computing’s Dark Age But
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Enter the GPU GPU = Graphics Proces
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Enter CUDA CUDA is a scalable paral
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110-240X © NVIDIA Corporation 2008
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GPUs Are Getting Faster, Faster ©
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© NVIDIA Corporation 2008 CUDA Pro
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Heterogeneous Programming CUDA = se
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Hierarchy of Concurrent Threads Thr
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Memory Hierarchy Sequential Kernels
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CUDA Language: C with Minimal Exten
Page 25 and 26: Example: Increment Array Elements C
Page 27 and 28: Example: Host Code // allocate host
Page 29 and 30: More on Memory Spaces Each thread c
Page 31 and 32: Compiling CUDA for NVIDIA GPUs Any
Page 33 and 34: Device Emulation Mode Pitfalls Emul
Page 35 and 36: Reduction Exercise At the end of ea
Page 37 and 38: Reduce 1: Blocking the Data Block I
Page 39 and 40: Reduce 1: Multi-Pass Reduction Bloc
Page 41 and 42: © NVIDIA Corporation 2008 CUDA Imp
Page 43 and 44: Hardware Implementation: A Set of S
Page 45 and 46: Hardware Implementation: Execution
Page 47 and 48: Host Synchronization All kernel lau
Page 49 and 50: Multiple CPU Threads and CUDA CUDA
Page 51 and 52: Performance Optimization Expose as
Page 53 and 54: Expose Parallelism: CPU/GPU Paralle
Page 55 and 56: Minimize CPU ↔ GPU Data Transfers
Page 57 and 58: Global Memory Reads/Writes Global m
Page 59 and 60: Coalesced Global Memory Accesses ©
Page 61 and 62: Non-Coalesced Global Memory Accesse
Page 63 and 64: Avoiding Non-Coalesced Accesses For
Page 65 and 66: Profiler Signals Events are tracked
Page 67 and 68: Back to Reduce Exercise: Profile wi
Page 69 and 70: Reduce 2 Thread IDs Block IDs Distr
Page 71 and 72: Maximize Use of Shared Memory Share
Page 73 and 74: Example: Square Matrix Multiplicati
Page 75: Example: Avoiding Non-Coalesced flo
Page 79 and 80: Example: Avoiding Non-Coalesced flo
Page 81 and 82: Execution Configuration: Constraint
Page 83 and 84: Execution Configuration: Heuristics
Page 85 and 86: Back to Reduce Exercise: Problem wi
Page 87 and 88: Parallel Reduction Complexity Takes
Page 89 and 90: Reduce 3: Go Ahead! Open up reduce\
Page 91 and 92: Arithmetic Instruction Throughput f
Page 93 and 94: Runtime Math Library There are two
Page 95 and 96: What You Need To Know FP64 instruct
Page 97 and 98: Mixed Precision Arithmetic Research
Page 99 and 100: Single Precision Floating Point ©
Page 101 and 102: Instruction Predication Comparison
Page 103 and 104: Shared Memory Is Banked Bandwidth o
Page 105 and 106: Bank Addressing Examples 2-way bank
Page 107 and 108: Back to Reduce Exercise: Problem wi
Page 109 and 110: Reduce 3: Bank Conflicts Showed for
Page 111 and 112: Reduce 4: Go Ahead! Open up reduce\
Page 113 and 114: Reduce 5: Unrolled Loop if (numThre
Page 115 and 116: Reduce 5: Final Unrolled Loop if (n
Page 117 and 118: Coming Up Soon CUDA 2.0 © NVIDIA C
Page 119 and 120: Extra Slides
Page 121 and 122: Applications - Condensed 3D image a
Page 123 and 124: Performance GPU Electromagnetic Fie
Page 125 and 126: EvolvedMachines 130X Speed up Brain
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nbody Astrophysics Astrophysics res
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A quick review device = GPU = set o
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Language Extensions: Function Type
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Language Extensions: Execution Conf
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Common Runtime Component Provides:
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Common Runtime Component: Mathemati
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Host Runtime Component Provides fun
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Host Runtime Component: Memory Mana
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Host Runtime Component: Interoperab
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Host Runtime Component: Error Handl
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Device Runtime Component: Mathemati
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Device Runtime Component: Texture F
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Compilation Any source file contain
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Role of Open64 Open64 compiler give
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CUDA Libraries CUBLAS CUFFT © NVID
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CUFFT Library Efficient implementat
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