Tutorial CUDA

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Reduction Example Reduce N values to a single one: © NVIDIA Corporation 2008 Sum(v 0, v 1, … , v N-2, v N-1) Min(v 0, v 1, … , v N-2, v N-1) Max(v 0, v 1, … , v N-2, v N-1) Common primitive in parallel programming Easy to implement in <strong>CUDA</strong> Less so to get it right Divided into 5 exercises throughout the day Each exercise illustrates one particular optimization strategy
Reduction Exercise At the end of each exercise, the result of the reduction computed on the device is checked for correctness © NVIDIA Corporation 2008 “Test PASSED” or “Test FAILED” is printed out to the console The goal is to replace the “TODO“ words in the code by the right piece of code to get “test PASSED”
Page 1 and 2: Tutorial CUDA Cyril Zeller NVIDIA D
Page 3 and 4: © NVIDIA Corporation 2008 GPU Comp
Page 5 and 6: Parallel Computing’s Dark Age But
Page 7 and 8: Enter the GPU GPU = Graphics Proces
Page 9 and 10: Enter CUDA CUDA is a scalable paral
Page 11 and 12: 110-240X © NVIDIA Corporation 2008
Page 13 and 14: GPUs Are Getting Faster, Faster ©
Page 15 and 16: © NVIDIA Corporation 2008 CUDA Pro
Page 17 and 18: Heterogeneous Programming CUDA = se
Page 19 and 20: Hierarchy of Concurrent Threads Thr
Page 21 and 22: Memory Hierarchy Sequential Kernels
Page 23 and 24: CUDA Language: C with Minimal Exten
Page 25 and 26: Example: Increment Array Elements C
Page 27 and 28: Example: Host Code // allocate host
Page 29 and 30: More on Memory Spaces Each thread c
Page 31 and 32: Compiling CUDA for NVIDIA GPUs Any
Page 33: Device Emulation Mode Pitfalls Emul
Page 37 and 38: Reduce 1: Blocking the Data Block I
Page 39 and 40: Reduce 1: Multi-Pass Reduction Bloc
Page 41 and 42: © NVIDIA Corporation 2008 CUDA Imp
Page 43 and 44: Hardware Implementation: A Set of S
Page 45 and 46: Hardware Implementation: Execution
Page 47 and 48: Host Synchronization All kernel lau
Page 49 and 50: Multiple CPU Threads and CUDA CUDA
Page 51 and 52: Performance Optimization Expose as
Page 53 and 54: Expose Parallelism: CPU/GPU Paralle
Page 55 and 56: Minimize CPU ↔ GPU Data Transfers
Page 57 and 58: Global Memory Reads/Writes Global m
Page 59 and 60: Coalesced Global Memory Accesses ©
Page 61 and 62: Non-Coalesced Global Memory Accesse
Page 63 and 64: Avoiding Non-Coalesced Accesses For
Page 65 and 66: Profiler Signals Events are tracked
Page 67 and 68: Back to Reduce Exercise: Profile wi
Page 69 and 70: Reduce 2 Thread IDs Block IDs Distr
Page 71 and 72: Maximize Use of Shared Memory Share
Page 73 and 74: Example: Square Matrix Multiplicati
Page 75 and 76: Example: Avoiding Non-Coalesced flo
Page 81 and 82: Execution Configuration: Constraint
Page 83 and 84: Execution Configuration: Heuristics
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Back to Reduce Exercise: Problem wi
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Parallel Reduction Complexity Takes
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Reduce 3: Go Ahead! Open up reduce\
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Arithmetic Instruction Throughput f
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Runtime Math Library There are two
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What You Need To Know FP64 instruct
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Mixed Precision Arithmetic Research
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Single Precision Floating Point ©
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Instruction Predication Comparison
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Shared Memory Is Banked Bandwidth o
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Bank Addressing Examples 2-way bank
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Back to Reduce Exercise: Problem wi
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Reduce 3: Bank Conflicts Showed for
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Reduce 4: Go Ahead! Open up reduce\
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Reduce 5: Unrolled Loop if (numThre
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Reduce 5: Final Unrolled Loop if (n
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Coming Up Soon CUDA 2.0 © NVIDIA C
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Extra Slides
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Applications - Condensed 3D image a
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Performance GPU Electromagnetic Fie
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EvolvedMachines 130X Speed up Brain
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nbody Astrophysics Astrophysics res
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A quick review device = GPU = set o
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Language Extensions: Function Type
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Language Extensions: Execution Conf
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Common Runtime Component Provides:
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Common Runtime Component: Mathemati
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Host Runtime Component Provides fun
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Host Runtime Component: Memory Mana
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Host Runtime Component: Interoperab
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Host Runtime Component: Error Handl
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Device Runtime Component: Mathemati
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Device Runtime Component: Texture F
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Compilation Any source file contain
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Role of Open64 Open64 compiler give
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CUDA Libraries CUBLAS CUFFT © NVID
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CUFFT Library Efficient implementat
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