Proyecto REX-2X - Radio Observatorio de Jicamarca
Proyecto REX-2X - Radio Observatorio de Jicamarca
Proyecto REX-2X - Radio Observatorio de Jicamarca
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ANEXO C Arquitectura interna <strong>de</strong>l FPGA<br />
DELAYLINES<br />
16FIFO<br />
ADAPTER<br />
MUX2<br />
RXDATA[15..0]<br />
INPUT<br />
I[15..0]<br />
O[15..0]<br />
DATA[15..0]<br />
O[15..0]<br />
I[15..0]<br />
O[15..0]<br />
DATA1[15..0]<br />
GCLK<br />
DV<br />
INPUT<br />
W2<br />
INPUT<br />
CLK<br />
LINE<br />
OUT<br />
WRREQ<br />
RDREQ<br />
FULL<br />
FULLINTINFIFO<br />
CTE<br />
19200<br />
GCLK<br />
16<br />
DATA0[15..0]<br />
CLOCK<br />
RESULT[15..0]<br />
OUTPUT<br />
DATAFIFO[15..0]<br />
WINDOW<br />
INPUT<br />
CLK<br />
SEL<br />
IQ<br />
SCLR<br />
16 BITS X 2 WORDS<br />
MUXSEL<br />
IQ<br />
INPUT<br />
DELAY 3<br />
IN OUT<br />
OR2<br />
CLK<br />
IN<br />
DELAY 3<br />
OUT<br />
CLK<br />
W2<br />
IQ<br />
DVF<br />
AND2<br />
OR2<br />
DFF<br />
PRN<br />
D Q<br />
CONTROLC1<br />
DELAY 3<br />
IN OUT<br />
NOT<br />
AND 2<br />
OUTPUT<br />
WRITEA<br />
TEST2<br />
WIRE<br />
OUTPUT<br />
ENA_EXT<br />
GCLK<br />
CLRN<br />
CLK<br />
DELAY 3<br />
IN OUT<br />
AND 2<br />
OUTPUT<br />
WRITEB<br />
OUTPUT<br />
MRESET<br />
CLK<br />
GND<br />
FULLINTINFIFO<br />
DELAY 4<br />
IN<br />
OUT<br />
CLEARFIFO<br />
CLK<br />
Figura 44 Arquitectura interna <strong>de</strong>l FPGA (1/3)<br />
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