3rd meeting of young researchers at UP 1 - IJUP - Universidade do ...

Polyphase filter with continuous parametric tuning
L. Malheiro 1 , P. Coke 1,2 , Cândido Duarte 1,2 , Vítor Grade Tavares 1,2 ,
and Pedro Guedes de Oliveira 1,2
1 Microelectronics Students’ Group, Department of Electrical and Computer Engineering, Faculty of
Engineering, University of Porto, Portugal.
2 INESC Porto, Faculty of Engineering, University of Porto, Portugal.
The world of wireless communication systems has been growing very rapidly. One aspect that
helped this development was the CMOS technology, allowing smaller devices with evermore
complexity. Nowadays, the pressure to build electronic systems with integrated circuits (ICs) is
growing, driven by the need for better portability and low-cost prizes with high-level of
integration, without compromising the performance. With this in mind, new receiver
architectures have been favored in detriment of the classical ones with a high intermediate
frequency (IF). In opposition, direct conversion and Low-IF receivers have been the focus of
investigation in the area of radio frequency (RF) microelectronics and CMOS technology.
In RF receivers, the image frequency is one of the biggest problems to deal during frequency
down-conversion. The polyphase filter is a way to avoid this problem, by suppression of the
image signal.
The main purpose of this work is then to develop a polyphase filter to be used in a Low-IF
receiver. This is a low-pass filter that is translated to a band-pass in the complex domain.
To diminish the area of the polyphase filter, the filter and hold (F&H) technique [1] is
employed. The F&H allows a circuit time constant to be several times lower than original
value needed to accomplish the specifications. For the low-pass prototype, a frequency cutoff
of -3 dB at 530-KHz [2] was chosen to keep all the necessary information from the desired
signal. This filter is then translated to 2-MHz, which is the value of the IF expected in the
receiver. Using a duty-cycle of 10% and a clock of 50- MHz, the physical designed time
constant was reduced 10 times while the performance of the polyphase filter is maintained. All
the testing was done using an Active-RC implementation of the filter.
The next steps in this research are the selection of the OTA type for a gm-C filter
implementation and, within, the filter architecture. To compensate for process deviations, a
tuning system for filter calibration will be performed. Finally, the design of the circuit will be
developed in a 0.35-µm CMOS process to prove the concept.
References:
[1] V.M. Grade Tavares, J.C. Principe, and J.G. Harris. “F&H filter: a novel ultra-low power discrete
time filter”, Electronics Letters, 35(15), pp. 1226–1227, Jul 1999.
[2] A.A. Emira and E. Sanchez-Sinencio, “A pseudo differential complex filter for Bluetooth with
frequency tuning”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal
Processing, 50(10), pp. 742–754, Oct. 2003.
3 rd meeting of young researchers at UP 169