IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

}
}
Figure 5 ) Protected Critical Section with Interrupt Masking
This method of protection is safe to use when the section being protected executes in very few
machine cycles, as is the case in this example. The concern is the hardware interrupt latency created
by this interrupt mask period. Masking interrupts for as long as 50 microseconds should be tolerable
on most systems. Caution must be used to assure that interrupts are always quickly re-enabled when
ever they are disabled!
Note that when the nature of the two tasks competing for access to the resource (Task_A and
Task_B in this example) dictates that one is higher priority than the other, only the lower priority task
requires the interrupt masking. It is not possible that the lower priority task could preempt the higher
priority task (unless the program design was to change task priorities dynamically somewhere).
RTOS Task Switch Lock
A further alternative to using semaphores to protect critical sections is to prevent task switching within
the critical section. This method is shown in the example below.
static unsigned long My_Ticker = 1 ;
void huge Task_A(void)
{
// Disable needed if Task_A is lower priority
RTX_Disable_Task_Scheduling() ; // Task switch lock
if (My_Ticker < 0x7FFFFFFFL)
{
My_Ticker++ ;
}
RTX_Enable_Task_Scheduling() ; // Resume task switching
}
void huge Task_B(void)
{
unsigned long ticker ;
// Disable needed if Task_B is lower priority
RTX_Disable_Task_Scheduling() ; // Task switch lock
ticker = My_Ticker ;
RTX_Enable_Task_Scheduling() ; // Resume task switching
if (ticker == 0)
{
Surprised_to_be_Here() ; // How did this happen?
}
}
Figure 6 ) Protected Critical Section with Task Lock
Hardware interrupts continue to be serviced during the task lock, so you can include more work now
within the critical section than was possible with the interrupt masking method. However, the task lock
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