IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

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DX Mask Bit 0 = 1 Enable INT0 Bit 1 = don't care Bit 2 = 1 Enable INT2 Bit 3 = 1 Enable INT3 Bit 4 = 1 Enable INT4 Bit 5 = 1 Enable INT5 Bit 6 = 1 Enable INT6 Bit 7..15 = don't care Return Value none Comments used pins: INT0, INT[2..6] excluded pins: if INT0: PIO13, TMROUT0, cascaded interrupt controller if INT2: PIO6, PCS2#, INTA#, PWD, hw flow control serial port 1 if INT3: PIO12, serial port 1 if INT4: PIO5, PCS3#, hw flow control serial port 1 if INT5: PIO1, DRQ0, default I²C-Bus pins if INT6: PIO0, DRQ1, default I²C-Bus pins Related Topics Top of list Index page Set Edge/Level Interrupt Mode Interrupt 0xA2 service 0x85: PFE: Enable External Timer Inputs/Outputs Parameters AH DX Enable external timer inputs (TMRIN0, TMRIN1) or timer outputs (TMROUT0, TMROUT1). Must be 0x85. Mode Return Value none Bit 0..1 = 10 Enable TMRIN0 = 11 Enable TMROUT0 Bit 2..3 = 10 Enable TMRIN1 = 11 Enable TMROUT1 Bit 4..15 = don't care Page 286 / 400
Comments If on a given timer the external input is selected, then that timer's external output is not available and viceversa. used pins: TMRIN[0..1], TMROUT[0..1] excluded pins: if TMRIN0: A0, PCS1#, PIO4, TMROUT0 if TMRIN1: A[1..2], PCS5#, TMROUT1 if TMROUT0: PIO13, INT0, cascaded interrupt controller, TMRIN0 if TMROUT1: A[1..2], PCS5#, TMRIN1, PIO3 Related Topics Top of list Index page HAL Initialize Timer Settings Interrupt 0xA2 service 0x86: PFE: Set Edge/Level Interrupt Mode Parameters AH AL DX Set edge/level interrupt mode for INT0, INT2, INT3, INT4. Must be 0x86. 1 = active high, level-sensitive interrupt 0 = low-to-high, edge-triggered interrupt Mask, bits set to designate interrupts affected: Bit 0 = INT0 Bit 1 = don't care Bit 2 = INT2 Bit 3 = INT3 Bit 4 = INT4 Bit 5..15 = don't care Return Value none Comments Default for all interrupts is edge-triggered mode. In each case (edge or level) the interrupt pins must remain high until they are acknowledged. Level-sensitive mode for INT5 / INT6 is not supported. The INT5 / INT6 interrupts operate only in edgetriggered mode. Page 287 / 400
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IPC@CHIP Documentation index - SC12
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available from the download area of
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IPC@CHIP Documentation Index Introd
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1. Timer procedures must be impleme
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Top of list Index page Usage of the
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Top of list Index page Using Hardwa
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Top of list Index page 3. Since @CH
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Top of list Index page End of docum
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IPC@CHIP Documentation Index COMMAN
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Index page TYPE file Type a file. T
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Example rd temp Top of list Index p
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Top of list Index page ALE Enable/d
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Related Topics Top of list Index pa
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Top of list Index page Initial BATC
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Comments Example Make sure that oth
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Comments Top of list Index page tas
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CHIP.INI Documentation - SC12 @CHIP
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STDIO ● SERIAL_EXT_DMA ● SERIAL
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The new mode is shown on the consol
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Top of list Index page IP ADD_DEFAU
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Top of list Index page [PPPCLIENT]
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Example: REMOTEADDRESS=192.168.205.
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IDLETIME=500 By default, PPP server
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Top of list Index page PPP server c
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Comments Example: INITRETRIES0=2 Th
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[PPPSERVER] CTRLTIMEOUTx=timeout in
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PPPSERVER [PPPSERVER] HANGUPANSWERx
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Top of list Index page PPPSERVER [P
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Example: Top of list Index page FTP
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Top of list Index page FTP PASSWORD
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WEB [WEB] TEMPPATH=Name of a tempor
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Top of list Index page WEB The cons
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WEB [WEB] SEC_PASSWORDx=Define a pa
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USERx=user Comments Top of list Ind
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TRACE [TRACE] INTNOTSUPP=0/1 Commen
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Top of list Index page SERIAL [SERI
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MEMGAP=Paragraphs Comments Sets a m
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IPC@CHIP Documentation Index CONFIG
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● Interrupt_0xA0_function_0x19:_C
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Top of list Index page AX = 0. (Thi
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Comments Top of list Index page DI
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ES:DX Pointer to a 16 byte memory a
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Index page Interrupt 0xA0 service 0
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Parameters AH Must be 0x15 Return V
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AH ES:DI Comments Must be 0x20. Add
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int iniPutString(char *sectionName,
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Get the IPC@CHIP device names Param
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Return Value Comments AL= 1 DX=0: S
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Parameters AH AL BX Must be 0x33. B
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void huge my_putstr(char * pch, int
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Index page Interrupt 0xA0 service 0
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Parameters AH ES:DX Top of list Ind
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● Interrupt_0xAC_function_0x0B:_A
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Socket descriptor Return Value DX =
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put into the buffer. The sender can
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The application sleeps for a specif
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Top of list Index page Interrupt 0x
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for the API_SEND function (or recv_
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a new connection. Related Topics To
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AH BX ES:DI 0x16 (= API_SETSOCKOPT)
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Interrupt 0xAC service 0x19: API_RE
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SocketInfo s[64]; int avail, i; ava
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Comments AX = -2 (=API_NOT_SUPPORTE
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Tests if PPP server is available in
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Index page Interrupt 0xAC service 0
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DS:SI CX 6 Get pointer to AtEntry d
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Bits of AX and DX contains the requ
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Parameters AH 0x74 (= TCPIP_STATIST
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Structure at [ES:DI] is filled with
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Parameters AH ES:DI 0x7A (= IP_USER
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This function is used to delete the
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CX Number of data structures in arr
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DS:SI Output Parameter: Pointer to
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For more detailed description see H
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BX CX ES:DI Number of available rec
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IPC@CHIP Documentation Index TCP/IP
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TCP/IP Application Developers Note
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ArpHeader Address Resolution Protoc
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Top of list Index page This buffer
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Comments This data structure and sp
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Comments These structures are only
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Comments unsigned long ipReasmOKs;
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typedef struct tag_ping_command { i
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The PPPDial structure is used durin
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Related Topics ❍ optionName=PPP_I
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SetSocketOption Comments This data
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Top of list Index page UdpMib Comme
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Programming client server applicati
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RTOS API - SC12 @CHIP-RTOS V1.10 IP
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AH BX 0 (=RTX_SLEEP_TIME) Sleep tim
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Return Value Comments DX=0 (always
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An out of range priority value (CX)
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Comments DX!=0 failure AX: contains
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BX ES:DI 0x19 (= RTX_RESERVE_RES) I
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Top of list Index page RTX_GET_SEM
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BX:SI Output Parameter: Pointer to
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ES:DI CX Output Parameter: Pointer
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Comments DX!=0 failure AX: contains
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The task name is not a null termina
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AH BX ES:DI DS:SI 0x40 (= RTX_CREAT
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Interrupt 0xAD service 0x43: RTX_WA
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ES:DI 0x46 (= RTX_FIND_EVENTGROUP)
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ES:DI Pointer to a 12 byte message
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Interrupt 0xAD service 0x55: RTX_FI
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Multitasking with @Chip-RTOS Some c
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ackground data base search in the e
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Suspended Free to run RTX_Resume_Ta
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Figure 1 ) Sleep Based Periodic Loo
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can potentially interrupt execution
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} } Figure 5 ) Protected Critical S
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RTOS Overview - SC12 @CHIP-RTOS V1.
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Time / Date Services The following
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Page 237 and 238: system's maximum number of availabl
Page 239 and 240: Prior to making the RTX_TASK_CREATE
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Page 243 and 244: name or void huge MyTimerProc(unsig
Page 245 and 246: IPC@CHIP Documentation Index @CHIP-
Page 247 and 248: RTOS Application Developers Note -
Page 249 and 250: DOS Interface Documentation - SC12
Page 251 and 252: Parameters AH DL 0x02 Character to
Page 253 and 254: AH 0x08 Return Value Comments Retur
Page 255 and 256: AH 0x19 Return Value AL = drive whe
Page 257 and 258: Top of list Index page Interrupt 0x
Page 259 and 260: Only ten DTA entries for user tasks
Page 261 and 262: Note: Top of list Index page In @CH
Page 263 and 264: Parameters AH CX 0x3C File attribut
Page 267 and 268: Top of list Index page Get/Set File
Page 269 and 270: BX DX Handle Device data Return Val
Page 271 and 272: A paragraph is 16 bytes in length.
Page 273 and 274: Comments Top of list Index page AX
Page 275 and 276: operations such as renaming, moving
Page 277 and 278: AL BX CX DX AL=0 to get the date an
Page 281 and 282: Hardware API - SC12 @CHIP-RTOS V1.1
Page 283 and 284: Top of list Index page if ALE is us
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Page 289 and 290: AH AL Must be 0x88. DRQ channel: 0
Page 291 and 292: AH ES:DI Must be 0x90. Pointer to a
Page 293 and 294: Comments 8 Bit data in ax, ax = (da
Page 295 and 296: Parameters AH DX BX CX Must be 0x83
Page 297 and 298: Top of list Index page RTX_SIGNAL_E
Page 299 and 300: none Related Topics Top of list Ind
Page 303 and 304: Related Topics Top of list Index pa
Page 305 and 306: instead be the frequency reported b
Page 307 and 308: Return Value none Comments Top of l
Page 309 and 310: Starts the DMA mode. After calling
Page 311 and 312: BX:SI ES:DI 1 = DRQ1 Output Paramet
Page 313 and 314: Return Value none Comments Call thi
Page 315 and 316: Hardware API Layers - SC12 @CHIP-RT
Page 317 and 318: This function initializes the I2C b
Page 319 and 320: AL CX Slave address, LSB:0 => Trans
Page 321 and 322: AH AL 0x8F PIO pin number, [0..13]
Page 323 and 324: AH ES:DI CX Must be 0x96 Pointer to
Page 325 and 326: I2C Bus and SPI API Updates - SC12
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Page 329 and 330: DX Port number: 0 for EXT, 1 for CO
Page 331 and 332: DX 0x08 Port number: 0 for EXT, 1 f
Page 333 and 334: AH AL DX 0x0F Bit mask describing r
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Top of list Index page transmitter.
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DX 2: short break (1 frame) 3: extr
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Top of list Index page send queue.
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User specific TCPIP Device driver -
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Generic example: int huge myDevSend
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Implementation of this function is
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} } Related Topics Top of list Inde
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{ result= Dev_Wait_DHCP_Complete(&m
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Index page Configuring the PPP Serv
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the call without waiting for the PP
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Top of list Index page Available Ex
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● Interrupt_0xAB_function_0x07:_C
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Return Value Comments DX =0 success
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Top of list Index page CGI_FINDNEXT
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IPC@CHIP Documentation Index CGI AP
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Top of list Index page @CHIP V0.92
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IPC@CHIP Documentation Index Data S
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Comments typedef struct { //*******
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IPC@CHIP Documentation Index CGI AP
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CGI Examples Available - SC12 @CHIP
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The interrupt declaration will moti
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Interrupt 0xAE service 0x01: DRIVER
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Handle from ACCESS_TYPE call 0x02 R
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AH 0x15 Return Value Carry flag:0,
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Top of list Index page ACCESS_TYPE
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Interrupt 0xB0 service 0x02: Deinst
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HW API handler latency RTX handler
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Scalable @CHIP-RTOS variants for th
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IPC@CHIP Documentation Index Progra
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IPC@CHIP Documentation Index Introd
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Top of list Index page TFTP server
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Top of list Index page Possible err
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IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

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