IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

Top of list
Index page
Interrupt 0xA2 service 0x83: PFE: Enable Programmable Chip Selects
Parameters
AH
DX
Enable chip selects PCS[0..3]#, PCS[5..6]#.
Must be 0x83.
Mask
Bit 0 = 1 Enable PCS0#, active when I/O address between 000h..0FFh
Bit 1 = 1 Enable PCS1#, active when I/O address between 100h..1FFh
Bit 2 = 1 Enable PCS2#, active when I/O address between 200h..2FFh
Bit 3 = 1 Enable PCS3#, active when I/O address between 300h..3FFh
Bit 4 = don't care
Bit 5 = 1 Enable PCS5#, active when I/O address between 500h..5FFh
Bit 6 = 1 Enable PCS6#, active when I/O address between 600h..6FFh
Bit 7..15 = don't care
Return Value
none
Comments
Top of list
Index page
used pins:
PCS[0..3]#, PCS[5..6]#
excluded pins:
if PCS0#: ALE (multiplexed address / data bus)
if PCS1#: A0, PIO4, TMRIN0
if PCS2#: PIO6, INT2, INTA#, PWD, hw flow control serial port 1,
cascaded interrupt controller
if PCS3#: PIO5, INT4, hw flow control serial port 1
if PCS5#: A[1..2], PIO3, TMROUT1, TMRIN1
if PCS6#: A[1..2], PIO2
Interrupt 0xA2 service 0x84: PFE: Enable External Interrupt Requests
Parameters
AH
Enable external interrupt requests INT[0], INT[2..6].
Must be 0x84.
Page 285 / 400