IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

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RTX_SIGNAL_EVENTS
RTX_SEND_MSG
RTX_START_TIMER
RTX_STOP_TIMER
RTX_REMOVE_TIMER
Important Notes:
A RTX ISR is slower than a normal ISR. RTX ISR are not recommended for INT5 or INT6 if DMA is
used by the Fossil serial ports interface, because the slower RTX ISR could result in UART receiver
character loss.
If you are using a RTX ISR for timer0, timer1, INT5 or INT6 there must not exist a normal ISR on the
system which enables the interrupts during its execution! Do not install a RTX ISR for NMI.!
Also important : The NMI function of the multifunction pin 17 (RESET/NMI/LINK_LED) of the
IPC@CHIP SC11/SC12/SC13 is for power fail purposes only. It is not possible to use NMI as a "normal"
interrupt pin like INT0 for generating interrupts. It can only be used as described in the IPC@CHIP
hardware documentation.
Interrupt 0xA1 service 0x85: HAL: Initialize Timer Settings
Parameters
AH
AL
DX
CX
Initialize the timer settings of timer0 or timer1.
Must be 0x85.
Timer
0=Timer0 / 1=Timer1
Mode
Bit 0: 0=run single time / 1=run continuous
Bit 1: 0=disable timer interrupt / 1=enable timer interrupt
Bit 2: 0=use internal clock / 1=use TMRIN pin as external clock
Bit 3..15: not used
Clock divider (maximum count value)
Return Value
none
Comments
The clock divider value serves as a comparator for the associated timer count. The timer count is a 16
bit value that is incremented by the processor internal clock (see HAL function 0x8A) or can also be
configured to increment based on the TMRIN0 or TMRIN1 external signals (see PFE function 0x85).
The TMROUT0 und TMROUT1 signals can be used to generate waveforms of various duty cycles. The
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