IPC@CHIP Documentation - SC12 @CHIP-RTOS V1.10

Related Topics
Top of list
Index page
Enable External Interrupt Requests
Interrupt 0xA2 service 0x87: PFE: Enable PWD Mode
Parameters
AH
Enable Pulse Width Demodulation (PWD)
Must be 0x87.
Return Value
none
Comments
Top of list
Index page
In PWD mode, TMRIN0, TMRIN1, INT2 and INT4 are configured internal to the
chip to support the detection of rising (INT2) and falling (INT4) edges on the PWD
input pin and to enable either timer0 when the signal is high or timer1 when
the signal is low. The INT4, TMRIN0 and TMRIN1 pins are not used in PWD mode
and so are available for use as PIO's.
The ISR for the INT2 and the INT4 interrupts should examine the current count of
the associated timer, timer1 for INT2 and timer0 for INT4, in order to determine
the pulse width. The ISR should then reset the timer count in preparation for the
next pulse.
Overflow conditions, where the pulse width is greater than the maximum count of the
timer, can be detected by monitoring the MaxCount bit in the associated timer or by
setting the timer to generated interrupt requests.
used pins:
PWD
excluded pins:
TMRIN0, TMRIN1, TMROUT0, TMROUT1, INT4, INT2
PCS2#, INTA#, PIO6, hw flow control serial port 1
Interrupt 0xA2 service 0x88: PFE: Enable External DMA
Parameters
Enables DRQ pin to start DMA transfer
Page 288 / 400