Chapter 23 Controller Area Network (CAN).pdf

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Functional Description www.ti.com 23.3.8.3.3 External Loopback Mode The external loopback mode is similar to the loopback mode; however, it includes the signal path from CAN core to Tx pin, the Tx pin itself, and the signal path from Tx pin back to CAN core. When external loopback mode is selected, the input of the CAN core is connected to the input buffer of the Tx pin. With this configuration, the Tx pin IO circuit can be tested. External loopback mode can be activated by setting bit ExL in test register to one. Figure 23-7 shows the connection of signals CAN_TX and CAN_RX to the CAN core in external loopback mode. NOTE: When loopback mode is active (LBack bit set), the ExL bit will be ignored. Figure 23-7. CAN Core in External Loopback Mode DCAN CAN_TX Pin CAN Core Rx Tx 23.3.8.3.4 Loopback Mode Combined With Silent Mode CAN_RX It is also possible to combine loopback mode and silent mode by setting bits LBack and Silent at the same time. This mode can be used for a “Hot Selftest,” i.e., the DCAN hardware can be tested without affecting the CAN network. In this mode, the CAN_RX pin is disconnected from the CAN core and no dominant bits will be sent on the CAN_TX pin. Figure 23-8 shows the connection of the signals CAN_TX and CAN_RX to the CAN core in case of the combination of loopback mode with silent mode. 4048 Controller Area Network (CAN) SPRUH73E–October 2011–Revised May 2012 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Pin
www.ti.com Functional Description Figure 23-8. CAN Core in Loop Back Combined With Silent Mode DCAN 23.3.8.3.5 Software Control of CAN_TX pin CAN_TX =1 • • Tx Rx CAN Core CAN_RX Four output functions are available for the CAN transmit pin CAN_TX. In addition to its default function (serial data output), the CAN_TX pin can drive constant dominant or recessive values, or it can drive the CAN sample point signal to monitor the CAN core’s bit timing. Combined with the readable value of the CAN_RX pin, this function can be used to check the physical layer of the CAN bus. The output mode of pin CAN_TX is selected by programming the test register bits Tx[1:0] as described in section Section 23.4.1.6. NOTE: The software control for the CAN_TX pin interferes with CAN protocol functions. For CAN message transfer or any of the test modes (loopback mode, external loopback mode or silent mode), the CAN_TX pin should operate in its default functionality. 23.3.9 Dual Clock Source Two clock domains are provided to the DCAN module: the peripheral synchronous clock domain (L3_SLOW_GCLK) as the general module clock source, and the peripheral asynchronous clock source domain (OSC0) provided to the CAN core (as clock source CAN_CLK) for generating the CAN bit timing. Both clock domains can be derived from the same clock source (so that L3_SLOW_GCLK = OSC0). For more information on how to configure the relevant clock source registers in the system module, see Chapter 8, Power and Clock Management. Between the two clock domains, a synchronization mechanism is implemented in the DCAN module in order to ensure correct data transfer. NOTE: If the dual clock functionality is used, then L3_SLOW_GCLK must always be higher or equal to CAN_CLK (OSC0) (derived from the asynchronous clock source), in order to achieve a stable functionality of the DCAN. Here also the frequency shift of the modulated L3_SLOW_GCLK has to be considered: f 0, L3_SLOW_GCLK(OCP) ± Δf FM, L3_SLOW_GCLK(OCP) ≥ f CANCLK NOTE: The CAN core has to be programmed to at least 8 clock cycles per bit time. To achieve a transfer rate of 1 MBaud when using the asynchronous clock domain as the clock source for CAN_CLK (OSC0), an oscillator frequency of 8MHz or higher has to be used. SPRUH73E–October 2011–Revised May 2012 Controller Area Network (CAN) Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated 4049
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