Chapter 23 Controller Area Network (CAN).pdf

Functional Description www.ti.com
23.3.10 Interrupt Functionality
Interrupts can be generated on two interrupt lines: DCANINT0 and DCANINT1. These lines can be
enabled by setting the IE0 and IE1 bits, respectively, in the CAN control register. The interrupts are level
triggered at the chip level.
The DCAN provides three groups of interrupt sources: message object interrupts, status change
interrupts, and error interrupts (see Figure 23-9 and Figure 23-10).
The source of an interrupt can be determined by the interrupt identifiers Int0ID/Int1ID in the interrupt
register (see Section 23.4.1.5). When no interrupt is pending, the register will hold the value zero.
Each interrupt line remains active until the dedicated field in the interrupt register DCAN INT (Int0ID /
Int1ID) again reach zero (this means the cause of the interrupt is reset), or until IE0 / IE1 are reset.
The value 0x8000 in the Int0ID field indicates that an interrupt is pending because the CAN core has
updated (not necessarily changed) the Error and Status register (DCAN ES). This interrupt has the highest
priority. The CPU can update (reset) the status bits WakeUpPnd, RxOk, TxOk and LEC by reading the
error and status register DCAN ES, but a write access of the CPU will never generate or reset an
interrupt.
Values between 1 and the number of the last message object indicates that the source of the interrupt is
one of the message objects, Int0ID resp. Int1ID will point to the pending message interrupt with the
highest priority. The Message Object 1 has the highest priority; the last message object has the lowest
priority.
An interrupt service routine that reads the message that is the source of the interrupt may read the
message and reset the message object’s IntPnd at the same time (ClrIntPnd bit in the IF1/IF2 command
register). When IntPnd is cleared, the interrupt register will point to the next message object with a
pending interrupt.
23.3.10.1 Message Object Interrupts
Message object interrupts are generated by events from the message objects. They are controlled by the
flags IntPND, TxIE and RxIE that are described in Section 23.3.18.1.
Message object interrupts can be routed to either DCANINT0 or DCANINT1 line, controlled by the
interrupt multiplexer register (DCAN INTMUX12 to DCAN INTMUX78), see Section 23.4.1.17.
23.3.10.2 Status Change Interrupts
The events WakeUpPnd, RxOk, TxOk and LEC in error and status register ( DCAN ES) belong to the
status change interrupts. The status change interrupt group can be enabled by bit in CAN control register.
If SIE is set, a status change interrupt will be generated at each CAN frame, independent of bus errors or
valid CAN communication, and also independent of the message RAM configuration.
Status change interrupts can only be routed to interrupt line DCAN0INT, which has to be enabled by
setting IE0 in the CAN control register.
NOTE: Reading the error and status register will clear the WakeUpPnd flag. If in global power-down
mode, the WakeUpPnd flag is cleared by such a read access before the DCAN module has
been waken up by the system, the DCAN may re-assert the WakeUpPnd flag, and a second
interrupt may occur.
23.3.10.3 Error Interrupts
The events PER, BOff and EWarn, monitored in the Error and Status register, DCAN ES, belong to the
error interrupts. The error interrupt group can be enabled by setting bit EIE in the CAN Control register.
Error interrupts can only be routed to interrupt line DCAN0INT, which has to be enabled by setting IE0 in
the CAN Control register.
4050 Controller Area Network (CAN) SPRUH73E–October 2011–Revised May 2012
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated