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Chapter 23 Controller Area Network (CAN).pdf

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D<strong>CAN</strong> Registers www.ti.com<br />

Figure <strong>23</strong>-21. Error Counter Register (D<strong>CAN</strong> ERRC)<br />

31 16<br />

Reserved<br />

R-0<br />

15 14 8 7 0<br />

RP REC[6:0] TEC[7:0]<br />

R-0 R-0 R-0<br />

LEGEND: R = Read only; -n = value after reset<br />

Bit Field Value Description<br />

Table <strong>23</strong>-16. Error Counter Register (D<strong>CAN</strong> ERRC) Field Descriptions<br />

31-16 Reserved 0 These bits are always read as 0. Writes have no effect.<br />

15 RP Receive error passive<br />

0 The receive error counter is below the error passive level.<br />

1 The receive error counter has reached the error passive level as defined in the <strong>CAN</strong> specification.<br />

14-8 REC[6:0] Receive error counter. Actual state of the receive error counter (values from 0 to 255).<br />

7-0 TEC[7:0] Transmit error counter. Actual state of the transmit error counter (values from 0 to 255).<br />

4084 <strong>Controller</strong> <strong>Area</strong> <strong>Network</strong> (<strong>CAN</strong>) SPRUH73E–October 2011–Revised May 2012<br />

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Copyright © 2011–2012, Texas Instruments Incorporated

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