Chapter 23 Controller Area Network (CAN).pdf
Chapter 23 Controller Area Network (CAN).pdf
Chapter 23 Controller Area Network (CAN).pdf
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Introduction www.ti.com<br />
<strong>23</strong>.1 Introduction<br />
<strong>23</strong>.1.1 D<strong>CAN</strong> Features<br />
The general features of the D<strong>CAN</strong> controller are:<br />
• Supports <strong>CAN</strong> protocol version 2.0 part A, B (ISO 11898-1)<br />
• Bit rates up to 1 MBit/s<br />
• Dual clock source<br />
• 16, 32, 64 or 128 message objects (instantiated as 64 on this device)<br />
• Individual identifier mask for each message object<br />
• Programmable FIFO mode for message objects<br />
• Programmable loop-back modes for self-test operation<br />
• Suspend mode for debug support<br />
• Software module reset<br />
• Automatic bus on after Bus-Off state by a programmable 32-bit timer<br />
• Message RAM parity check mechanism<br />
• Direct access to Message RAM during test mode<br />
• <strong>CAN</strong> Rx / Tx pins configurable as general purpose IO pins<br />
• Two interrupt lines (plus additional parity-error interrupt line)<br />
• RAM initialization<br />
• DMA support<br />
<strong>23</strong>.1.2 Unsupported D<strong>CAN</strong> Features<br />
The D<strong>CAN</strong> module in this device does not support GPIO pin mode. All GPIO functionality is mapped<br />
through the GPIO modules and muxed at the pins. GPIO pin control signals from the D<strong>CAN</strong> modules are<br />
not connected.<br />
4038 <strong>Controller</strong> <strong>Area</strong> <strong>Network</strong> (<strong>CAN</strong>) SPRUH73E–October 2011–Revised May 2012<br />
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Copyright © 2011–2012, Texas Instruments Incorporated
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