Chapter 23 Controller Area Network (CAN).pdf

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23.3.12 Parity Check Mechanism
The DCAN provides a parity check mechanism to ensure data integrity of message RAM data. For each
word (32 bits) in message RAM, one parity bit will be calculated. The formation of the different words is
according to the message RAM representation in RDA mode, see Section 23.3.18.4.
Parity information is stored in the message RAM on write accesses and will be checked against the stored
parity bit from message RAM on read accesses.
The Parity check functionality can be enabled or disabled by PMD bit field in the CAN control register.
In case of disabled parity check, the parity bits in message RAM will be left unchanged on write access to
data area and no check will be done on read access.
If parity checking is enabled, parity bits will be automatically generated and checked by the DCAN. The
parity bits could be read in debug/suspend mode (see Section 23.3.18.3) or in RDA mode (see
Section 23.3.18.4). However, direct write access to the parity bits is only possible in these two modes with
parity check disabled.
A parity bit will be set, if the modulo-2-sum of the data bits is 1. This definition is equivalent to: The parity
bit will be set, if the number of 1 bits in the data is odd.
NOTE: The parity scheme is tied to even parity at the device level.
23.3.12.1 Behavior on Parity Error
On any read access to message RAM (e.g., during start of a CAN frame transmission), the parity of the
message object will be checked. If a parity error is detected, the PER bit in the error and status register
will be set. If error interrupts are enabled, an interrupt would also be generated. In order to avoid the
transmission of invalid data over the CAN bus, the D bit of the message object will be reset.
The message object data can be read by the host CPU, independently of parity errors. Thus, the
application has to ensure that the read data is valid, e.g., by immediately checking the parity error code
register (DCAN PERR) on parity error interrupt.
NOTE: During RAM initialization, no parity check will be done.
23.3.12.2 Parity Testing
Testing the parity mechanism can be done by enabling the bit RamDirectAccess ( RDA) and manually
writing the parity bits directly to the dedicated RAM locations. With this, data and parity bits could be
checked when reading directly from RAM.
NOTE: If parity check was disabled, the application has to ensure correct parity bit handling in order
to prevent parity errors later on when parity check is enabled.
4054 Controller Area Network (CAN) SPRUH73E–October 2011–Revised May 2012
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