Fast Fourier Transforms on Motorola's Digital Signal Processors

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Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 7-1 Figure A-1 Figure B-1 Figure B-2 Illustrations Bergland algorithm has only log2(N)-1 passes and one more addition and subtraction 6-5 (a) Butterfly of Bergland Algorithm with W = 1 (b) Butterfly of Bergland Algorithm with W ≠ 1 6-6 C language code that generates Bergland order tables 6-7 Computation of the real-input, DIT FFT 6-17 DSP56001 assembly code that calculates energy of DFT coefficients by single parameter 6-19 Double buffering input data so that data input can work with the FFT program concurrently 6-21 Block diagram of the double buffering technique 6-22 The flow diagram of an 8-point discrete cosine transform 7-4 Optimized Complex FFT for the DSP96002 A-1 <strong>Fast</strong>er real FFT for the DSP96002 B-1 Real FFT for DSP56001/2 B-5 MOTOROLA xi
Table 8-1 Table 8-2 Table 8-3 Table 8-4 Tables 1024-Point Complex FFT on Floating-Point DSPs 8-4 1024-Point Real Input FFT on Floating-Point DSPs 8-5 1024-Point Complex FFT on Fixed-Point DSPs 8-6 1024-Point Real Input FFT on Fixed-Point DSPs 8-7 MOTOROLA xiii
Page 1 and 2: Motorola’s High-Performance DSP T
Page 3 and 4: SECTION 1 Definition and History SE
Page 5 and 6: SECTION 5 Optimizing Performance of
Page 7 and 8: APPENDIX B Real-Valued Input FFT Ta
Page 9: Figure 4-3 Figure 4-4 Figure 4-5 Fi
Page 13 and 14: When interpreted as an infinite sum
Page 15 and 16: 2. Pattern-Based ⎯ Many problems
Page 17 and 18: In summary, the basic nature of the
Page 19 and 20: ecause: j2πfnT+j2πn e T - ⎛ ---
Page 21 and 22: 2.2 Windowing and Windowing Effects
Page 23 and 24: xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
Page 25 and 26: Note that many textbooks simply def
Page 27 and 28: “Since there are two independent
Page 29 and 30: appropriately called the decimation
Page 31 and 32: x(0) x(4) Figure 3-4 Decimation-in-
Page 33 and 34: Binary Index 000 x(0) 001 010 011 1
Page 35 and 36: 3.4 The Decimation-in- Frequency Ra
Page 37 and 38: DSP56001/2 and DSP96002 hardware fe
Page 39 and 40: 4. Bit-reversed addressing mode 5.
Page 41 and 42: 4.3 Complexity of a Radix-2 DIT FFT
Page 43 and 44: The data paths are 24 bits wide, th
Page 45 and 46: The kernel shown in Figure 4-4 exec
Page 47 and 48: ;Alters Program Control Registers ;
Page 49 and 50: PORT A CLK 4 ADDRESS 32 Control 19
Page 51 and 52: ;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
Page 53 and 54: 5 5 7 ADDRESS Sigma Delta Codec PI/
Page 55 and 56: limits its results to those bits. T
Page 57 and 58: flow in the FFT calculation is to s
Page 59 and 60: of the sine table, 256 points. Howe
Page 61 and 62:
normal_order=output_pointer; bitrev
Page 63 and 64:
A′ A CW c BW b DW c W b = + + ( +
Page 65 and 66:
;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 67 and 68:
Ar′ = Ar + Br + ( Dr + Cr) Ai′
Page 69 and 70:
“Optimization saves . . . 2067 in
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plexity to practical complexity ref
Page 73 and 74:
5.1.2 Optimization for Fast
Page 75 and 76:
3. pass. This change results in lon
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5.2 Example of Optimization 5.2.1 F
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Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82:
The fully optimized 1024-point comp
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6.1 Real-Valued Input FFT Algorithm
Page 85 and 86:
The twiddle factors appear to be in
Page 87 and 88:
X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
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takes four points in and four point
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Z( k) = DFT[ z( n) ] = DFT[ x( n) +
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F( k) a real sequence with N points
Page 95 and 96:
Eight multiplications, five additio
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further: 1. Since the input data is
Page 99 and 100:
6.4 The Goertzel Algorithm Previous
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The power of magnitude of the DFT c
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SSI or HI The double buffering is i
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“To implement Eqn. 7-1, a two dim
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F( k) where: N - 1 2c( k) ---------
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7.2.2 Two Dimensional DCT A one dim
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facturer may offer a higher perform
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8.2.1.1 Complex FFT on Floating-Poi
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8.2.2 FFT on Fixed-Point DSPs As me
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“Motorola's family of digital sig
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APPENDIX A Fully Optimized Complex
Page 121 and 122:
;**********************************
Page 123 and 124:
;**********************************
Page 125 and 126:
movem 2,m5 movem 2,m7 move #data,r0
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; ------------ NORMAL RADIX-2 BUTTE
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nop nop jmp * end ; ; Sine-Cosine T
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; Input signal for FFT rfft56.asm a
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move #POINTS/2-1,m0 ;modulo address
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; r0->A,r1->B,r4->A’,r5->B’,r6-
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_inner_pass do n3,_end_grp ;do grou
Page 139 and 140:
APPENDIX B Real-Valued Input FFT B.
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count set 0 dup points/2 dc @cos(@c
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B.2 Real FFT for DSP56001/2 ; ; Thi
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dup points/4 dc @cos(@cvf(count)*fr
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macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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