Fast Fourier Transforms on Motorola's Digital Signal Processors

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is twice as large as true values. Ten instruction cycles is the minimum requirement. In practice, one instruction in the loop for data saving is included. On the DSP96002, since the FMPY||ADD||SUB instruction is available, eight instructions are enough to perform a computation such as Eqn. 6-10. In AP- PENDIX A more details about implementation such as memory map, program length, twiddle factors, and data size are presented. The overall performance of the algorithm is determined by the time required to calculate an N/2 complex FFT plus the time for separating manipulations. CFFT( N ⁄ 2) + S × N⁄ 4 where: S = 11 for the DSP56001 S = 8 for the DSP96002 Eqn. 6-12 6.3 Real-Valued Input FFT Algorithm 3 In most practical situations, the data to be analyzed by the FFT is real and is usually obtained from a single analog-to-digital (A/D) converter.This knowledge can be exploited in several ways to increase the speed of the FFT calculation even MOTOROLA 6-15
further: 1. Since the input data is real, there is no need to multiply, add, or subtract the imaginary parts. 2. Use can be made of symmetries within the FFT: X N ( k ) = X ∗ N ( N – k ) Eqn. 6-13 When x(nT) is real, * denotes complex conjugate. Clearly, not all of the frequency points need to be calculated, as many of them can be obtained by taking a simple complex conjugate of other, previously computed points. Taking a complex conjugate can be easily achieved by moving the same values to different memory locations, after taking the negative of the value which goes to Y memory (imaginary part). Figure 6-5 shows the procedure for a 16-point, real FFT in greater detail. A real-input FFT routine is available for the DSP56001/2, which executes in 1.01 ms using a 40-MHz clock. This also includes the amount of time necessary to bring in 1024 sampled data points from an external A/D converter. Because of the fast interrupt capability of the DSP56001/2, data sampling creates very little overhead. As a result, the maximum sampling rate at which a 1024point real FFT can be executed equals: 1024 F smax 1.01 10 3 – = ----------------------------- = 1.014( MHz ) × Comparing this with the sampling rate of 3.3 kHz mentioned in SECTION 3.1 Motivation, a more than 300-fold improvement is obtained by carefully optimizing the <strong>Fourier</strong> transform algorithm! 6-16 MOTOROLA
Page 1 and 2:
Motorola’s High-Performance DSP T
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SECTION 1 Definition and History SE
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SECTION 5 Optimizing Performance of
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APPENDIX B Real-Valued Input FFT Ta
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Figure 4-3 Figure 4-4 Figure 4-5 Fi
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Table 8-1 Table 8-2 Table 8-3 Table
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When interpreted as an infinite sum
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2. Pattern-Based ⎯ Many problems
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In summary, the basic nature of the
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ecause: j2πfnT+j2πn e T - ⎛ ---
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2.2 Windowing and Windowing Effects
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xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
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Note that many textbooks simply def
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“Since there are two independent
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appropriately called the decimation
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x(0) x(4) Figure 3-4 Decimation-in-
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Binary Index 000 x(0) 001 010 011 1
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3.4 The Decimation-in- Frequency Ra
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DSP56001/2 and DSP96002 hardware fe
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4. Bit-reversed addressing mode 5.
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4.3 Complexity of a Radix-2 DIT FFT
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The data paths are 24 bits wide, th
Page 45 and 46: The kernel shown in Figure 4-4 exec
Page 47 and 48: ;Alters Program Control Registers ;
Page 49 and 50: PORT A CLK 4 ADDRESS 32 Control 19
Page 51 and 52: ;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
Page 53 and 54: 5 5 7 ADDRESS Sigma Delta Codec PI/
Page 55 and 56: limits its results to those bits. T
Page 57 and 58: flow in the FFT calculation is to s
Page 59 and 60: of the sine table, 256 points. Howe
Page 61 and 62: normal_order=output_pointer; bitrev
Page 63 and 64: A′ A CW c BW b DW c W b = + + ( +
Page 65 and 66: ;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 67 and 68: Ar′ = Ar + Br + ( Dr + Cr) Ai′
Page 69 and 70: “Optimization saves . . . 2067 in
Page 71 and 72: plexity to practical complexity ref
Page 73 and 74: 5.1.2 Optimization for Fast
Page 75 and 76: 3. pass. This change results in lon
Page 77 and 78: 5.2 Example of Optimization 5.2.1 F
Page 79 and 80: Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82: The fully optimized 1024-point comp
Page 83 and 84: 6.1 Real-Valued Input FFT Algorithm
Page 85 and 86: The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95: Eight multiplications, five additio
Page 99 and 100: 6.4 The Goertzel Algorithm Previous
Page 101 and 102: The power of magnitude of the DFT c
Page 103 and 104: SSI or HI The double buffering is i
Page 105 and 106: “To implement Eqn. 7-1, a two dim
Page 107 and 108: F( k) where: N - 1 2c( k) ---------
Page 109 and 110: 7.2.2 Two Dimensional DCT A one dim
Page 111 and 112: facturer may offer a higher perform
Page 113 and 114: 8.2.1.1 Complex FFT on Floating-Poi
Page 115 and 116: 8.2.2 FFT on Fixed-Point DSPs As me
Page 117 and 118: “Motorola's family of digital sig
Page 119 and 120: APPENDIX A Fully Optimized Complex
Page 121 and 122: ;**********************************
Page 123 and 124: ;**********************************
Page 125 and 126: movem 2,m5 movem 2,m7 move #data,r0
Page 127 and 128: ; ------------ NORMAL RADIX-2 BUTTE
Page 129 and 130: nop nop jmp * end ; ; Sine-Cosine T
Page 131 and 132: ; Input signal for FFT rfft56.asm a
Page 133 and 134: move #POINTS/2-1,m0 ;modulo address
Page 135 and 136: ; r0->A,r1->B,r4->A’,r5->B’,r6-
Page 137 and 138: _inner_pass do n3,_end_grp ;do grou
Page 139 and 140: APPENDIX B Real-Valued Input FFT B.
Page 141 and 142: count set 0 dup points/2 dc @cos(@c
Page 143 and 144: B.2 Real FFT for DSP56001/2 ; ; Thi
Page 145 and 146: dup points/4 dc @cos(@cvf(count)*fr
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macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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