Fast Fourier Transforms on Motorola's Digital Signal Processors

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For example, if there are 1024-point complex inputs, 8 x 256 + 4 x 256 x 14 =16,384 instructions may be required to improve performance by 11% if compared with 1024-point radix-2 DIT FFT. Here assume, TRIV = 8 and BFLY = 14 since eight ADD||SUB and six ADD instructions are theoretically required for such a butterfly calculation. One important fact is that BFLY, (the number of instruction cycles for butterfly calculation) in a radix-4 DIT FFT must be less than 16, otherwise, there is no advantage for using radix-4 over radix-2. Due to an insufficient number of operations code, FMPY// ADD//SUB instruction only works with destination registers D0 to D3 on the DSP96002. 4.10.2 Radix-4 DIF Butterfly Core Using the same derivation, a radix-4 DIF butterfly can be obtained. Although the number of multiplications and additions is the same as the radix-4 DIT butterfly, the sequence of data appears differently. Eqn. 4-9 shows an expanded form of the radix-4 DIF butterfly. Eighteen instructions are used to code the radix-4 DIF butterfly. MOTOROLA 4-31
Ar′ = Ar + Br + ( Dr + Cr) Ai′ = Ai + Bi + ( Di + Ci) c c Cr′ = [ ( Ar – Br) – ( Dr – Cr) ]W r + [ ( Ai – Bi) – ( Di – Ci) ]W i c c Ci′ = [ ( Ai – Bi) – ( Di – Ci) ]W r – [ ( Ar – Br) – ( Dr – Cr) ] W i b b Br′ = [ ( Ar + Bi) – ( Di + Cr) ]W r + [ ( Ai – Br) + ( Dr – Ci) ]W i b b Bi′ = [ ( Ai – Br) + ( Dr – Ci) ]W r – [ ( Ar + Bi) – ( Di + Cr) ] W i d d Dr′ = [ ( Ar – Bi) + ( Di – Cr) ]W r + [ ( Ai + Bi) – ( Dr + Ci) ]W i d d Ci′ = [ ( Ai + Br) – ( Di + Cr) ]W r – [ ( Ar – Bi) + ( Di – Ci) ]W i 4.11 Inverse FFT Eqn. 4-8 The Inverse <strong>Fast</strong> <strong>Fourier</strong> Transform (IFFT) is defined in Eqn. 4-9 x( n) N– 1 1 --- X N∑ k = 0 k ( )ej2πkn N ⁄ = Eqn. 4-9 The differences between inverse FFTs and forward FFTs are in the scaling factor, N, and the conjugated twiddle factors. A common method of implementing the IFFT is to change the sign of the sine table values and use the FFT subroutine to get the IFFT. Alternatively, one can swap real and imaginary parts, use swapped inputs to the regular 4-32 MOTOROLA
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Motorola’s High-Performance DSP T
Page 3 and 4:
SECTION 1 Definition and History SE
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SECTION 5 Optimizing Performance of
Page 7 and 8:
APPENDIX B Real-Valued Input FFT Ta
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Figure 4-3 Figure 4-4 Figure 4-5 Fi
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Table 8-1 Table 8-2 Table 8-3 Table
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When interpreted as an infinite sum
Page 15 and 16: 2. Pattern-Based ⎯ Many problems
Page 17 and 18: In summary, the basic nature of the
Page 19 and 20: ecause: j2πfnT+j2πn e T - ⎛ ---
Page 21 and 22: 2.2 Windowing and Windowing Effects
Page 23 and 24: xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
Page 25 and 26: Note that many textbooks simply def
Page 27 and 28: “Since there are two independent
Page 29 and 30: appropriately called the decimation
Page 31 and 32: x(0) x(4) Figure 3-4 Decimation-in-
Page 33 and 34: Binary Index 000 x(0) 001 010 011 1
Page 35 and 36: 3.4 The Decimation-in- Frequency Ra
Page 37 and 38: DSP56001/2 and DSP96002 hardware fe
Page 39 and 40: 4. Bit-reversed addressing mode 5.
Page 41 and 42: 4.3 Complexity of a Radix-2 DIT FFT
Page 43 and 44: The data paths are 24 bits wide, th
Page 45 and 46: The kernel shown in Figure 4-4 exec
Page 47 and 48: ;Alters Program Control Registers ;
Page 49 and 50: PORT A CLK 4 ADDRESS 32 Control 19
Page 51 and 52: ;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
Page 53 and 54: 5 5 7 ADDRESS Sigma Delta Codec PI/
Page 55 and 56: limits its results to those bits. T
Page 57 and 58: flow in the FFT calculation is to s
Page 59 and 60: of the sine table, 256 points. Howe
Page 61 and 62: normal_order=output_pointer; bitrev
Page 63 and 64: A′ A CW c BW b DW c W b = + + ( +
Page 65: ;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 69 and 70: “Optimization saves . . . 2067 in
Page 71 and 72: plexity to practical complexity ref
Page 73 and 74: 5.1.2 Optimization for Fast
Page 75 and 76: 3. pass. This change results in lon
Page 77 and 78: 5.2 Example of Optimization 5.2.1 F
Page 79 and 80: Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82: The fully optimized 1024-point comp
Page 83 and 84: 6.1 Real-Valued Input FFT Algorithm
Page 85 and 86: The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95 and 96: Eight multiplications, five additio
Page 97 and 98: further: 1. Since the input data is
Page 99 and 100: 6.4 The Goertzel Algorithm Previous
Page 101 and 102: The power of magnitude of the DFT c
Page 103 and 104: SSI or HI The double buffering is i
Page 105 and 106: “To implement Eqn. 7-1, a two dim
Page 107 and 108: F( k) where: N - 1 2c( k) ---------
Page 109 and 110: 7.2.2 Two Dimensional DCT A one dim
Page 111 and 112: facturer may offer a higher perform
Page 113 and 114: 8.2.1.1 Complex FFT on Floating-Poi
Page 115 and 116: 8.2.2 FFT on Fixed-Point DSPs As me
Page 117 and 118:
“Motorola's family of digital sig
Page 119 and 120:
APPENDIX A Fully Optimized Complex
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;**********************************
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;**********************************
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movem 2,m5 movem 2,m7 move #data,r0
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; ------------ NORMAL RADIX-2 BUTTE
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nop nop jmp * end ; ; Sine-Cosine T
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; Input signal for FFT rfft56.asm a
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move #POINTS/2-1,m0 ;modulo address
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; r0->A,r1->B,r4->A’,r5->B’,r6-
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_inner_pass do n3,_end_grp ;do grou
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APPENDIX B Real-Valued Input FFT B.
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count set 0 dup points/2 dc @cos(@c
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B.2 Real FFT for DSP56001/2 ; ; Thi
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dup points/4 dc @cos(@cvf(count)*fr
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macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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