Fast Fourier Transforms on Motorola's Digital Signal Processors

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4.4.2 DIT Butterfly Kernel on DSP56001 The parallel architecture and the instruction set of Motorola's DSP56001/2 lend themselves particularly well to the radix-2 DIT FFT computation.The DIT butterfly equations are programmed on Motorola's DSP56001/2 as given below: A’ r = Ar + Br Wr + Bi Wi A’ i = Ai + Bi Wr- Br Wi B’ r = 2Ar - A’ r B’ i = 2Ai - A’ i Eqn. 4-2 where: i represents an imaginary component r represents a real component ‘ symbolizes output items The basic butterfly “core” is implemented by assembly language in Figure 4-4. Note that the previous DSP56001/2 equations are written in this particular form such that the instruction to shift left and subtract accumulators (SUBL) can be used. This SUBL instruction allows efficient implementation of the DIT butterfly in a two-accumulator ALU. ;r0 ➧ A ;r1 ➧ B ;r4 ➧ C ;r5 ➧ D mac x1,y0,b y:(r1)+,y1 ;A i - B r W i ➧ b,B i ➧ y1 macr -x0,y1,b a,x:(r5)+ y:(r0),a ;A i - B rW i + B iW r➧ b,A i ➧ a subl b,a x: (r0),b b,y:(r4) ;2A i - b ➧ a,A r ➧ b mac -x1,x0,b x: (r0)+,a a,y:(r5) ;A r + B rW r ➧ b,A r ➧ a macr -y1,y0,b x: (r1),x1 ;A r + B rW r + B iW i ➧ b,B r ➧ x1 subl b,a b,x:(r4)+ y:(r0),b ;2Ar - b ➧ a,A i ➧ b Figure 4-4 The radix-2, DIT butterfly kernel on the DSP56001/2 MOTOROLA 4-9
The kernel shown in Figure 4-4 executes in six instruction cycles, or a total of 12 clock cycles. This is made possible because of the parallel architecture of the DSP56001/2, which allows up to two data ALU operations (multiply/accumulate) in parallel with two data moves to/from memory and two pointer updates in a single instruction cycle. The dual data spaces X and Y with the appropriate X and Y buses are ideally suited for complex arithmetic; the real components are stored in X memory and the imaginary components are stored in Y memory. The simplest way of combining all of the butterflies into a complete program is shown in Figure 4-1. The FFT diagram is first divided into FFT passes. On each pass, the data is fetched from memory, the butterfly calculations are done, and the results are moved back out to memory. It is easily shown that there are log2N passes. Within each pass, the butterflies cluster in groups. From one pass to the next, the number of groups doubles, while the number of butterflies per group is divided by two. Note that the twiddle factors are the same for all butterflies within each group, and that the order of the twiddle factors from one group to the next is bit-reversed. This is easily implemented on the DSP56001/2 by setting the appropriate modifier register (m6) equal to zero and the offset register (n6) equal to N/4 (= coefficient table size/2), such that the twiddle factors are addressed in bit-reversed manner. This gives rise to the simple, triple-nested DO loop program shown in Figure 4-5. The outer DO loop steps through passes, the middle loop goes through all of the groups within a pass, and the inner loop cycles through all of the butterflies inside a group. The 4-10 MOTOROLA
Page 1 and 2: Motorola’s High-Performance DSP T
Page 3 and 4: SECTION 1 Definition and History SE
Page 5 and 6: SECTION 5 Optimizing Performance of
Page 7 and 8: APPENDIX B Real-Valued Input FFT Ta
Page 9 and 10: Figure 4-3 Figure 4-4 Figure 4-5 Fi
Page 11 and 12: Table 8-1 Table 8-2 Table 8-3 Table
Page 13 and 14: When interpreted as an infinite sum
Page 15 and 16: 2. Pattern-Based ⎯ Many problems
Page 17 and 18: In summary, the basic nature of the
Page 19 and 20: ecause: j2πfnT+j2πn e T - ⎛ ---
Page 21 and 22: 2.2 Windowing and Windowing Effects
Page 23 and 24: xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
Page 25 and 26: Note that many textbooks simply def
Page 27 and 28: “Since there are two independent
Page 29 and 30: appropriately called the decimation
Page 31 and 32: x(0) x(4) Figure 3-4 Decimation-in-
Page 33 and 34: Binary Index 000 x(0) 001 010 011 1
Page 35 and 36: 3.4 The Decimation-in- Frequency Ra
Page 37 and 38: DSP56001/2 and DSP96002 hardware fe
Page 39 and 40: 4. Bit-reversed addressing mode 5.
Page 41 and 42: 4.3 Complexity of a Radix-2 DIT FFT
Page 43: The data paths are 24 bits wide, th
Page 47 and 48: ;Alters Program Control Registers ;
Page 49 and 50: PORT A CLK 4 ADDRESS 32 Control 19
Page 51 and 52: ;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
Page 53 and 54: 5 5 7 ADDRESS Sigma Delta Codec PI/
Page 55 and 56: limits its results to those bits. T
Page 57 and 58: flow in the FFT calculation is to s
Page 59 and 60: of the sine table, 256 points. Howe
Page 61 and 62: normal_order=output_pointer; bitrev
Page 63 and 64: A′ A CW c BW b DW c W b = + + ( +
Page 65 and 66: ;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 67 and 68: Ar′ = Ar + Br + ( Dr + Cr) Ai′
Page 69 and 70: “Optimization saves . . . 2067 in
Page 71 and 72: plexity to practical complexity ref
Page 73 and 74: 5.1.2 Optimization for Fast
Page 75 and 76: 3. pass. This change results in lon
Page 77 and 78: 5.2 Example of Optimization 5.2.1 F
Page 79 and 80: Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82: The fully optimized 1024-point comp
Page 83 and 84: 6.1 Real-Valued Input FFT Algorithm
Page 85 and 86: The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95 and 96:
Eight multiplications, five additio
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further: 1. Since the input data is
Page 99 and 100:
6.4 The Goertzel Algorithm Previous
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The power of magnitude of the DFT c
Page 103 and 104:
SSI or HI The double buffering is i
Page 105 and 106:
“To implement Eqn. 7-1, a two dim
Page 107 and 108:
F( k) where: N - 1 2c( k) ---------
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7.2.2 Two Dimensional DCT A one dim
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facturer may offer a higher perform
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8.2.1.1 Complex FFT on Floating-Poi
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8.2.2 FFT on Fixed-Point DSPs As me
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“Motorola's family of digital sig
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APPENDIX A Fully Optimized Complex
Page 121 and 122:
;**********************************
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;**********************************
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movem 2,m5 movem 2,m7 move #data,r0
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; ------------ NORMAL RADIX-2 BUTTE
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nop nop jmp * end ; ; Sine-Cosine T
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; Input signal for FFT rfft56.asm a
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move #POINTS/2-1,m0 ;modulo address
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; r0->A,r1->B,r4->A’,r5->B’,r6-
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_inner_pass do n3,_end_grp ;do grou
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APPENDIX B Real-Valued Input FFT B.
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count set 0 dup points/2 dc @cos(@c
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B.2 Real FFT for DSP56001/2 ; ; Thi
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dup points/4 dc @cos(@cvf(count)*fr
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macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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