Fast Fourier Transforms on Motorola's Digital Signal Processors

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Table 8-1 shows that the Motorola DSP96002 performs the fastest 1024-point complex FFT. The Analog Devices’ ADSP21020 performs almost as well as the DSP96002. The main factor that makes these two DSPs so fast in calculating the FFT is the special instruction “MPY||ADD||SUB”. Supported by this instruction, the DSP96002 needs only four instruction cycles to perform one radix 2 butterfly, and the DSP21020 needs only fourteen instruction cycles to do one radix 4 butterfly. However, the DSP96002 has 2x512 data words on the chip and it features two onchip DMA controllers. The on-chip memory and DMA controllers are extremely important features in implementing real-time data acquisition and control. The lack of peripherals and memory on the DSP21020 forces it into the position of competing with RISC chips. Although the DSP21020 requires lower cost SRAM for zero wait states interface, the program memory has to be 48-bits wide which negates the system cost benefits of using slow memory. 8.2.1.2 Real FFT on Floating-Point DSPs Table 8-2 1024-Point Real Input FFT on Floating-Point DSPs DSPs 96002 1 TIC40 2 TIC30 3 AT&T32C 4 Icycle (ns) 50 50 60 80 Total Icycles 11600 20396 31317 26300 Total Time (ms) 1. See RFFT96T.asm on the Motorola DSP Bulletin Board (Dr. BuB). 2. Texas Instruments, TMSC4x User’s Guide 0.58 1.01984 1.879 2.106 3. Texas Instruments, Digital Signal Processing Applications with the TMS320 Family. 4. AT&T DSP32C User’s Manual. MOTOROLA 8-5
8.2.2 FFT on Fixed-Point DSPs As mentioned previously, scaling must be performed on the fixed-point DSPs to prevent overflow in the intermediate stage of calculation. The following benchmarks, either complex or real FFT, assume that each input data has been divided by the number of the FFT. 8.2.2.1 Complex Input FFT Table 8-3 1024-Point Complex FFT on Fixed-Point DSPs DSPs 56001/2 1 AD2100A 2 TIC25 3 TIC50 3 56156 4 Icycle (ns) 60/50 80 80 35 33 Algorithm DIT DIT DIT DIT DIT Radix 2 4 2 2 2 P Memory (word) Data Memory (word) SIN/COS table Instruction length (bit) 234 222 158 4N 4N 2N 2N 4N N/2 3N/2 5N/4 5N/4 N 24 24 16 16 16 Total Icycles 29949 34625 113487 82761 46373 Total Time (ms) 1.79694/ 1.49745 2.77 9.079 2.8967 1.53031 1. See CFFT56.asm on the Motorola DSP Bulletin Board (Dr. BuB). 2. R.Meyer and K. Schwartz “FFT Implementation on DSP Chips — Theory and Practice” ICASSP, 1990. 3. Texas Instruments TMS320 DSP Family Benchmarks. 4. See CFFT156.asm on the Motorola DSP Bulletin Board (Dr. BuB). 8-6 MOTOROLA
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Motorola’s High-Performance DSP T
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SECTION 1 Definition and History SE
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SECTION 5 Optimizing Performance of
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APPENDIX B Real-Valued Input FFT Ta
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Figure 4-3 Figure 4-4 Figure 4-5 Fi
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Table 8-1 Table 8-2 Table 8-3 Table
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When interpreted as an infinite sum
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2. Pattern-Based ⎯ Many problems
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In summary, the basic nature of the
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ecause: j2πfnT+j2πn e T - ⎛ ---
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2.2 Windowing and Windowing Effects
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xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
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Note that many textbooks simply def
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“Since there are two independent
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appropriately called the decimation
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x(0) x(4) Figure 3-4 Decimation-in-
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Binary Index 000 x(0) 001 010 011 1
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3.4 The Decimation-in- Frequency Ra
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DSP56001/2 and DSP96002 hardware fe
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4. Bit-reversed addressing mode 5.
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4.3 Complexity of a Radix-2 DIT FFT
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The data paths are 24 bits wide, th
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The kernel shown in Figure 4-4 exec
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;Alters Program Control Registers ;
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PORT A CLK 4 ADDRESS 32 Control 19
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;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
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5 5 7 ADDRESS Sigma Delta Codec PI/
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limits its results to those bits. T
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flow in the FFT calculation is to s
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of the sine table, 256 points. Howe
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normal_order=output_pointer; bitrev
Page 63 and 64: A′ A CW c BW b DW c W b = + + ( +
Page 65 and 66: ;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 67 and 68: Ar′ = Ar + Br + ( Dr + Cr) Ai′
Page 69 and 70: “Optimization saves . . . 2067 in
Page 71 and 72: plexity to practical complexity ref
Page 73 and 74: 5.1.2 Optimization for Fast
Page 75 and 76: 3. pass. This change results in lon
Page 77 and 78: 5.2 Example of Optimization 5.2.1 F
Page 79 and 80: Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82: The fully optimized 1024-point comp
Page 83 and 84: 6.1 Real-Valued Input FFT Algorithm
Page 85 and 86: The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95 and 96: Eight multiplications, five additio
Page 97 and 98: further: 1. Since the input data is
Page 99 and 100: 6.4 The Goertzel Algorithm Previous
Page 101 and 102: The power of magnitude of the DFT c
Page 103 and 104: SSI or HI The double buffering is i
Page 105 and 106: “To implement Eqn. 7-1, a two dim
Page 107 and 108: F( k) where: N - 1 2c( k) ---------
Page 109 and 110: 7.2.2 Two Dimensional DCT A one dim
Page 111 and 112: facturer may offer a higher perform
Page 113: 8.2.1.1 Complex FFT on Floating-Poi
Page 117 and 118: “Motorola's family of digital sig
Page 119 and 120: APPENDIX A Fully Optimized Complex
Page 121 and 122: ;**********************************
Page 123 and 124: ;**********************************
Page 125 and 126: movem 2,m5 movem 2,m7 move #data,r0
Page 127 and 128: ; ------------ NORMAL RADIX-2 BUTTE
Page 129 and 130: nop nop jmp * end ; ; Sine-Cosine T
Page 131 and 132: ; Input signal for FFT rfft56.asm a
Page 133 and 134: move #POINTS/2-1,m0 ;modulo address
Page 135 and 136: ; r0->A,r1->B,r4->A’,r5->B’,r6-
Page 137 and 138: _inner_pass do n3,_end_grp ;do grou
Page 139 and 140: APPENDIX B Real-Valued Input FFT B.
Page 141 and 142: count set 0 dup points/2 dc @cos(@c
Page 143 and 144: B.2 Real FFT for DSP56001/2 ; ; Thi
Page 145 and 146: dup points/4 dc @cos(@cvf(count)*fr
Page 147 and 148: macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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