Fast Fourier Transforms on Motorola's Digital Signal Processors

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macr y1,y0,b x:(r1),x1 ;b=Ar+BrWr+BiWi=Ar’,x1=nGBr subl b,a b,x:(r4)+n4 y:(r0),b ;a=2Ar-Ar’=Br’,save Ar’, ;b=nGAi,r4->nGAr mac -x1,x0,b y:(r1)+,y1 ;b=Ai-BrWr,y1=Bi,r1->nGBi macr -y0,y1,b a,x:(r5)+n5y:(r0),a ;b=Ai-BrWr-BiWi=Ai’, ;save prev. Br’,a=Ai,r5->nGBi subl b,a x:(r0),b b,y:(r4) ;a=2Ai-Ai’=Bi’,b=Ar,save Ai’ mac -x1,y0,b x:(r0)+, a,y:(r5) ;b=Ar-BrWi,a=Ar,save Bi’,r0->nGAi macr y1,x0,b x:(r1),x1 ;b=Ar-BrWi+BiWr=Ar’,x1=nBr subl b,a b,x:(r4)+ y:(r0),b ;a=2Ar-Ar’=Br’, ;save Ar’,b=nAi,r4->nGAr mac -x1,x0,b y:(r1)+n1,y1 ;b=Ai-BrWr,y1=Bi,r1->nGBi macr -y0,y1,b a,x:(r5)+ y:(r0),a ;b=Ai-BrWi-BiWr=Ai’, ;save prev. Br’,a=Ai,r5->Bi subl b,a x:(r0),b b,y:(r4) ;a=2Ai-Ai’=Bi’,b=Ar,save Ai’ mac -x1,y0,b x:(r0)+n0,a a,y:(r5) ;b=Ar-BrWi,a=Ar, ;save Bi’,r0->nGAi macr y1,x0,b x:(r1),x1 y:(r6),y0 ;b=Ar-BrWi+BiWr=Ar’, ;x1=nBr,y0=nWi subl b,a b,x:(r4)+n4 y:(r0),b ;a=2Ar-Ar’=Br’,save Ar’, ;b=nAi,r4->nGAr _n_last move a,x:(r5) rts _last move x:(r5),a y:(r0),b ;a=something,b=Ai move x:(r1),x1 y:(r6),y0 ;x1=Br,y0=Wi do n2,_end_last ;do last pass, internal to external mac -x1,y0,b x:(r6)+,x0 y:(r1)+n1,y1 ;b=Ai-BrWi,x0=Wr,y1=Bi, r1->nGBi macr x0,y1,b a,x:(r5)+n5 y:(r0),a ;b=Ai-BrWi+BiWr=Ai’, ;save prev. Br’,a=Ai subl b,a x:(r0),b b,y:(r4) ;a=2Ai-Ai’=Bi’,b=Ar,save Ai’ mac x1,x0,b x:(r0)+n0,a a,y:(r5) ;b=Ar+BrWr,a=Ar,save Bi’,r0->nGAi macr y1,y0,b x:(r1),x1 ;b=Ar+BrWr+BiWi=Ar’,x1=nGBr subl b,a b,x:(r4)+n4 y:(r0),b ;a=2Ar-Ar’=Br’, ;save Ar’,b=nGAi,r4->nGAr mac -x1,x0,b y:(r1)+n1,y1 ;b=Ai-BrWr,y1=Bi,r1->nGBi macr -y0,y1,b a,x:(r5)+n5 y:(r0),a ;b=Ai-BrWr-BiWi=Ai’, ;save prev. Br’,a=Ai,r5->Bi subl b,a x:(r0),b b,y:(r4) ;a=2Ai-Ai’=Bi’,b=Ar,save Ai’ mac -x1,y0,b x:(r0)+n0,a a,y:(r5) ;b=Ar-BrWi,a=Ar,save Bi’,r0->nGAi macr y1,x0,b x:(r1),x1 y:(r6),y0 ;b=Ar-BrWi+BiWr=Ar’, ;x1=nBr,y0=nWi subl b,a b,x:(r4)+n4 y:(r0),b ;a=2Ar-Ar’=Br’, ;save Ar’,b=nAi,r4->nGAr _end_last move a,x:(r5) rts _end_FFT endm Figure A-1 Optimized Complex FFT for the DSP96002 (sheet 20 of 20) A-20 MOTOROLA
APPENDIX B Real-Valued Input FFT B.1 <strong>Fast</strong>er real FFT for the DSP96002 page 132,60,1,1 opt mex ;******************************************* ;Motorola Austin DSP Operation 20 August 1992 ;******************************************* ;Test program for DSP96002 rfft96.asm ;************************************************************************** ; 1024 real-valued inputs ; Maximum sample rate: 0.58 ms at 40.0 MHz ; Memory Size: Prog:141 + 32 words ; ; Data:2*1024 words(idata+odata) + 256 words (twiddle factor) ; Number of clock cycles: 23200 (11600 instruction cycles) ; Clock Frequency: 40.0MHz ; Instruction cycle time: 50.ns ;************************************************************************** ; ; Real-Valued Input Radix 2 Cooley-Tukey Decimation in Time FFT ; ; ; normally ordered input data ; normally ordered output data ; ;**************************************************************************** ; Equates Section ;**************************************************************************** RESET equ $00000000 ; reset isr MAIN equ $00000100 ; main routine points equ 512 ;points=real data number /2 passes equ 9 ;log2(points)=passes idata equ $0 odata equ $1000 coef equ $800 Figure B-1 <strong>Fast</strong>er real FFT for the DSP96002 (sheet 1 of 4) MOTOROLA B-1
Page 1 and 2:
Motorola’s High-Performance DSP T
Page 3 and 4:
SECTION 1 Definition and History SE
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SECTION 5 Optimizing Performance of
Page 7 and 8:
APPENDIX B Real-Valued Input FFT Ta
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Figure 4-3 Figure 4-4 Figure 4-5 Fi
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Table 8-1 Table 8-2 Table 8-3 Table
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When interpreted as an infinite sum
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2. Pattern-Based ⎯ Many problems
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In summary, the basic nature of the
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ecause: j2πfnT+j2πn e T - ⎛ ---
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2.2 Windowing and Windowing Effects
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xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
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Note that many textbooks simply def
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“Since there are two independent
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appropriately called the decimation
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x(0) x(4) Figure 3-4 Decimation-in-
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Binary Index 000 x(0) 001 010 011 1
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3.4 The Decimation-in- Frequency Ra
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DSP56001/2 and DSP96002 hardware fe
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4. Bit-reversed addressing mode 5.
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4.3 Complexity of a Radix-2 DIT FFT
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The data paths are 24 bits wide, th
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The kernel shown in Figure 4-4 exec
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;Alters Program Control Registers ;
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PORT A CLK 4 ADDRESS 32 Control 19
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;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
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5 5 7 ADDRESS Sigma Delta Codec PI/
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limits its results to those bits. T
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flow in the FFT calculation is to s
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of the sine table, 256 points. Howe
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normal_order=output_pointer; bitrev
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A′ A CW c BW b DW c W b = + + ( +
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;r0->A,r4->B, r1->C, r6->D; ;r1->A
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Ar′ = Ar + Br + ( Dr + Cr) Ai′
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“Optimization saves . . . 2067 in
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plexity to practical complexity ref
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5.1.2 Optimization for Fast
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3. pass. This change results in lon
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5.2 Example of Optimization 5.2.1 F
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Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
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The fully optimized 1024-point comp
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6.1 Real-Valued Input FFT Algorithm
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The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95 and 96: Eight multiplications, five additio
Page 97 and 98: further: 1. Since the input data is
Page 99 and 100: 6.4 The Goertzel Algorithm Previous
Page 101 and 102: The power of magnitude of the DFT c
Page 103 and 104: SSI or HI The double buffering is i
Page 105 and 106: “To implement Eqn. 7-1, a two dim
Page 107 and 108: F( k) where: N - 1 2c( k) ---------
Page 109 and 110: 7.2.2 Two Dimensional DCT A one dim
Page 111 and 112: facturer may offer a higher perform
Page 113 and 114: 8.2.1.1 Complex FFT on Floating-Poi
Page 115 and 116: 8.2.2 FFT on Fixed-Point DSPs As me
Page 117 and 118: “Motorola's family of digital sig
Page 119 and 120: APPENDIX A Fully Optimized Complex
Page 121 and 122: ;**********************************
Page 123 and 124: ;**********************************
Page 125 and 126: movem 2,m5 movem 2,m7 move #data,r0
Page 127 and 128: ; ------------ NORMAL RADIX-2 BUTTE
Page 129 and 130: nop nop jmp * end ; ; Sine-Cosine T
Page 131 and 132: ; Input signal for FFT rfft56.asm a
Page 133 and 134: move #POINTS/2-1,m0 ;modulo address
Page 135 and 136: ; r0->A,r1->B,r4->A’,r5->B’,r6-
Page 137: _inner_pass do n3,_end_grp ;do grou
Page 141 and 142: count set 0 dup points/2 dc @cos(@c
Page 143 and 144: B.2 Real FFT for DSP56001/2 ; ; Thi
Page 145 and 146: dup points/4 dc @cos(@cvf(count)*fr
Page 147 and 148: macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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