Fast Fourier Transforms on Motorola's Digital Signal Processors

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For high-end applications, the DSP96002 provides full IEEE standard floating-point arithmetic for negligible roundoff errors. In addition to providing standard IEEE exception handling capabilities, the results obtained in the DSP96002 are portable across many applications that use the standard, such as high-level language simulations, data buses, etc. Motorola's family of digital signal processors, combined with Motorola's data conversion parts (see Reference 12), provide a complete, cost-efficient solution to frequency domain problems; from low-end small-size FFT applications, to high-end instrumentation and computer workstations for scientific computing. ■ Acknowledgments The authors wish to thank Professor Raimund Meyer and K.Schwarz in University Erlangen in F.R Germany who provided the optimized 1024-point complex FFT program for the DSP96002; Vitus Ho in Dell Computer, Austin, Texas, who provided two dimensional FFT and DCT code for the DSP96002. Also a lot of thanks to Roman Robles in Motorola DSP Applications group for valuable comments and the C language code of Bergland’s algorithm. 9-2 MOTOROLA
APPENDIX A Fully Optimized Complex FFT A.1 Optimized Complex FFT for the DSP96002 ;***************************************************************************** ; * ; RMAXS.ASM : START PROGRAM FOR THE FFT MACRO RMAX.ASM. * ; THIS FILE SHOWS HOW TO CONFIGURE MOTOROLAS DSP96002 * ; TO USE THE FAST COMPLEX FFT. * ; TWIDDLE FACTORS IN R4TAB1.ASM * ; * ; WRITTEN BY : KARL SCHWARZ, RAIMUND MEYER 10.11.89 * ; * ; LEHRSTUHL FUER NACHRICHTENTECHNIK * ; UNIVERSITAET ERLANGEN-NUERNBERG * ; * ;***************************************************************************** include ‘r4tab1’ include‘rmax’ points equ 1024 ; FFT-length, only 1024 possible passes equ 10 ; ld(points) data equ $800 ; input data, normal order odata equ $C00 ; output data, normal order tab4 equ $1000 ; start of radix-4 twiddle factors ; 766 complex values) r4 tab1 tab4 org p:$100 move #$008A0000,x:$FFFFFFFD ; zero wait states in BCRB move #$008A0000,x:$FFFFFFFE ; zero wait states in BCRA move #$0000FFFF,x:$FFFFFFFC ; X port A, Y and P port B in PSR ;Upper three moves won’t count for the benchmark, ;only for initializing the simulator or the DSP. ;They show how to configure the device. Figure A-1 Optimized Complex FFT for the DSP96002 (sheet 1 of 20) MOTOROLA A-1
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Motorola’s High-Performance DSP T
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SECTION 1 Definition and History SE
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SECTION 5 Optimizing Performance of
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APPENDIX B Real-Valued Input FFT Ta
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Figure 4-3 Figure 4-4 Figure 4-5 Fi
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Table 8-1 Table 8-2 Table 8-3 Table
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When interpreted as an infinite sum
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2. Pattern-Based ⎯ Many problems
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In summary, the basic nature of the
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ecause: j2πfnT+j2πn e T - ⎛ ---
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2.2 Windowing and Windowing Effects
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xf () x(nT) 1 0.9 0.8 0.7 0.6 0.5 0
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Note that many textbooks simply def
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“Since there are two independent
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appropriately called the decimation
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x(0) x(4) Figure 3-4 Decimation-in-
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Binary Index 000 x(0) 001 010 011 1
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3.4 The Decimation-in- Frequency Ra
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DSP56001/2 and DSP96002 hardware fe
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4. Bit-reversed addressing mode 5.
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4.3 Complexity of a Radix-2 DIT FFT
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The data paths are 24 bits wide, th
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The kernel shown in Figure 4-4 exec
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;Alters Program Control Registers ;
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PORT A CLK 4 ADDRESS 32 Control 19
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;r0 ➨ A ;r1 ➨ B ;r4 ➨ C ;r5
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5 5 7 ADDRESS Sigma Delta Codec PI/
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limits its results to those bits. T
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flow in the FFT calculation is to s
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of the sine table, 256 points. Howe
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normal_order=output_pointer; bitrev
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A′ A CW c BW b DW c W b = + + ( +
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;r0->A,r4->B, r1->C, r6->D; ;r1->A
Page 67 and 68: Ar′ = Ar + Br + ( Dr + Cr) Ai′
Page 69 and 70: “Optimization saves . . . 2067 in
Page 71 and 72: plexity to practical complexity ref
Page 73 and 74: 5.1.2 Optimization for Fast
Page 75 and 76: 3. pass. This change results in lon
Page 77 and 78: 5.2 Example of Optimization 5.2.1 F
Page 79 and 80: Pass 0 1 2 3 4 5 6 7 8 A B C D W=(1
Page 81 and 82: The fully optimized 1024-point comp
Page 83 and 84: 6.1 Real-Valued Input FFT Algorithm
Page 85 and 86: The twiddle factors appear to be in
Page 87 and 88: X=A+jB Y=C+jD X’=A+C+j(D+B) - Y
Page 89 and 90: takes four points in and four point
Page 91 and 92: Z( k) = DFT[ z( n) ] = DFT[ x( n) +
Page 93 and 94: F( k) a real sequence with N points
Page 95 and 96: Eight multiplications, five additio
Page 97 and 98: further: 1. Since the input data is
Page 99 and 100: 6.4 The Goertzel Algorithm Previous
Page 101 and 102: The power of magnitude of the DFT c
Page 103 and 104: SSI or HI The double buffering is i
Page 105 and 106: “To implement Eqn. 7-1, a two dim
Page 107 and 108: F( k) where: N - 1 2c( k) ---------
Page 109 and 110: 7.2.2 Two Dimensional DCT A one dim
Page 111 and 112: facturer may offer a higher perform
Page 113 and 114: 8.2.1.1 Complex FFT on Floating-Poi
Page 115 and 116: 8.2.2 FFT on Fixed-Point DSPs As me
Page 117: “Motorola's family of digital sig
Page 121 and 122: ;**********************************
Page 123 and 124: ;**********************************
Page 125 and 126: movem 2,m5 movem 2,m7 move #data,r0
Page 127 and 128: ; ------------ NORMAL RADIX-2 BUTTE
Page 129 and 130: nop nop jmp * end ; ; Sine-Cosine T
Page 131 and 132: ; Input signal for FFT rfft56.asm a
Page 133 and 134: move #POINTS/2-1,m0 ;modulo address
Page 135 and 136: ; r0->A,r1->B,r4->A’,r5->B’,r6-
Page 137 and 138: _inner_pass do n3,_end_grp ;do grou
Page 139 and 140: APPENDIX B Real-Valued Input FFT B.
Page 141 and 142: count set 0 dup points/2 dc @cos(@c
Page 143 and 144: B.2 Real FFT for DSP56001/2 ; ; Thi
Page 145 and 146: dup points/4 dc @cos(@cvf(count)*fr
Page 147 and 148: macr y1,y0,a y:(r4),y0 ;a=Wi*H2r-Wr
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Fast Fourier Transforms on Motorola's Digital Signal Processors

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