Image sensor datasheet (PDF)

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AC OPERATING CONDITIONS Clock Levels Description Symbol Minimum Nominal Maximum Units Notes Vertical CCD Clocks - High φV1H, φV2H +14.5 +14.7 +15.0 V 1 Vertical CCD Clocks - Mid φV1M, φV2M -0.5 -0.2 0.0 V 1 Vertical CCD Clocks - Low φV1L, φV2L -9.0 -8.0 -7.0 V 1 Horizontal CCD Clocks - High φH1H, φH2H +1.0 +2.0 +3.0 V 1 Horizontal CCD Clocks - Low φH1L, φH2L -10.0 -9.0 -8.0 V 1 Reset Clock - High φRH +7.0 +8.0 +9.0 V Reset Clock - Low φRL +2.0 +3.0 +4.0 V For Electronic Shutter Pulse Only VES (SUB) +40 +42 +45 V 2 Notes: 1. For best results, the CCD clock swings must be maintained at (or greater than) the values indicted by the nominal level conditions noted above. 2. This pulse, used only for electronic shutter mode operation, is applied to the substrate, as described in the Electronic Shutter section of this document. Dynamic resistance is 3kΩ and typical DC current is 3 mA at VSUB = 40V. Clock Line Capacitances Description Symbol Typical Units Vertical CCD Clocks - Well C φV1, φV2 (A, B combined) 10 nF VCCD Clock Phase 1 - VCCD Clock Phase 2 C φV1 - φV2 (A, B combined) 1.5 nF Horizontal CCD Clocks - Well C φH1, φH2 150 pF HCCD Clock Phase 1 - HCCD Clock Phase 2 C φH1 - φH2 60 pF Reset Clock - Well C φR 5 pF For Electronic Shutter Pulse C SUB 400 pF Timing Requirements Description Symbol Minimum Nominal Maximum Units Notes Vertical High Level Duration t φVH 5 17 20 µsec Vertical Transfer Time t φV 2.8 µsec Vertical Pedestal Delay t φVPD 10 µsec Horizontal Delay t φHD 5.3 µsec Reset Duration t φR 15 20 25 nsec 1 Horizontal Clock Frequency f φH 14.32 MHz Line Time t L 63.5 µsec Vertical Delay t φVD 200 nsec Horizontal Delay with Electronic Shutter t φHVES 1.0 µsec Clamp Delay t cd nsec 2 Sample Delay t sd nsec 2 Electronic Shutter Pulse Duration t es 4 5 µsec 3 Notes: 1. The rising edge of φR should be coincident with the rising edge of φH2, within ±5 nsec. 2. The clamp delay and sample delay should be adjusted for optimum results. 3. This pulse is used only with electronic shuttering and should not be used during horizontal readout. The electronic shutter pulse should be hidden in the horizontal retrace interval. ©Eastman Kodak Company, 2006 www.kodak.com/go/imagers Revision 2.0 MTD/PS-0660 p14
Frame Timing 525 φV1 (A & B) φV2 (A & B) Integration Time t int VES (SUB) (Electronic Shutter Mode Only) tL φV1 (A & B) φV2 (A & B) 1 Line Time = tL = 63.5 µsec tφVPD tφVH tφVPD 523 524 525 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vertical Overclocking Figure 9: Frame Timing Note : When no electronic shutter is used, the integration time is equal to the frame time. ©Eastman Kodak Company, 2006 www.kodak.com/go/imagers Revision 2.0 MTD/PS-0660 p15
Page 1 and 2: DEVICE PERFORMANCE SPECIFICATION Re
Page 3 and 4: TABLE OF FIGURES Figure 1: Sensor A
Page 5 and 6: DEVICE DESCRIPTION ARCHITECTURE φV
Page 7 and 8: ELECTRONIC SHUTTER The KAI-0373 pro
Page 9 and 10: PERFORMANCE IMAGING PERFORMANCE All
Page 11 and 12: Defect Definitions All values are d
Page 13: OPERATION MAXIMUM RATINGS Absolute
Page 17 and 18: Pixel Timing 1 count = 1 Pixel 69.8
Page 19 and 20: STORAGE AND HANDLING Climatic Requi
Page 21 and 22: DIE TO PACKAGE ALIGNMENT Figure 15:
Page 23 and 24: GLASS TRANSMISSION 10 0 90 80 70 Tr
Page 25 and 26: ORDERING INFORMATION Available Part
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Image sensor datasheet (PDF)

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