Image sensor datasheet (PDF)

PIN DESCRIPTION AND PHYSICAL ORIENTATION
OG 1
24
φV2A
φR
2
23
φV1A
VRD
3
22
φV2B
VSS
4
Pixel 1,1
21
φV1B
VLG
5
20
WELL
VOUT
6
19
SUB
VDD
7
18
LTSH
WELL
8
17
φV1A
φH2
9
16
φV2A
φH1
10
15
φV1B
ESD
11
14
φV2B
NC
12
13
ESD
Pin 1 Locator
Side View Of Package
1 2 3 4 5
Figure 5: Pin Description
Pin Name Description Pin Name Description
1 OG Output Gate 24 φV2A Vertical CCD Clock – Phase 2
2 φR Reset Clock 23 φV1A Vertical CCD Clock – Phase 1
3 VRD Reset Drain 22 φV2B Vertical CCD Clock – Phase 2
4 VSS Output Amplifier Return 21 φV1B Vertical CCD Clock – Phase 1
5 VLG Output Amplifier Load Gate 20 WELL Ground
6 VOUT Video Output 19 SUB Substrate
7 VDD Output Amplifier Supply 18 LTSH Lightshield
8 WELL Ground 17 φV1A Vertical CCD Clock – Phase 1
9 φH2 Horizontal CCD Clock – Phase 2 16 φV2A Vertical CCD Clock – Phase 2
10 φH1 Horizontal CCD Clock – Phase 1 15 φV1B Vertical CCD Clock – Phase 1
11 ESD Horizontal ESD Well 14 φV2B Vertical CCD Clock – Phase 2
12 NC No Connect 13 ESD Vertical ESD Well
Notes:
1. The pins are on a 0.100” spacing
2. Pins 14, 16, 22, and 24 must be connected together – only one Phase 2 clock driver is required.
3. Pins 15, 17, 21, and 23 must be connected together – only one Phase 1 clock driver is required.
©Eastman Kodak Company, 2006 www.kodak.com/go/imagers Revision 2.0 MTD/PS-0660 p8