CME136686LX Hardware Manual - RTD Embedded Technologies ...

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System Recovery Loading Default BIOS Settings The default BIOS can be restored either by using the “Load Defaults” option in the BIOS, or by installing jumper JP5 (see Figure on page 93). In most cases, the easiest way to load default settings is by setting them in the BIOS. For other unique cases, jumper JP5 provides an alternative method of restoring the BIOS settings. To restore the default BIOS settings with jumper JP5, follow the procedure below. 1. Remove power from the system. 2. Install JP5. 3. Apply power to the system. The cpuModule will then load its default settings. Note that the multi-color LED will be magenta (purple) if power is applied while JP5 is installed. 4. Reboot and press Delete to enter BIOS Setup. 5. Save the BIOS settings and exit, allowing the system to boot to the FSBR. 6. The next time the system is powered, the BIOS Setup will be configured to use the default settings. Booting to the Fail Safe Boot ROM (FSBR) If your system is in configuration that will not allow it to boot, the Fail Safe Boot ROM is a minimal build of ROM-DOS which can be booted to for system debugging. To boot to the FSBR, follow the instructions below. 1. Reboot the system and press Delete to enter BIOS Setup. 2. In the Boot menu, select Bootup Settings Configuration, and change RTD Fail Safe Boot to Enabled. 3. Save the BIOS settings and exit. If you are unable to enter the BIOS Setup, an alternate method is to use JP5 as described below: 1. Remove power from the system. 2. Install JP5. This will force the cpuModule to boot using the default BIOS configuration. 3. Apply power to the system. The cpuModule will then boot to the Fail Safe Boot ROM image. Note that the multi-color LED will be red if power is applied while JP5 is installed. 4. Press the Delete key to enter Setup, or allow the cpuModule to boot to Failsafe 86 CME136686LX cpuModule BDM-610000065 Rev C
Basic Interrupt Information for Programmers An interrupt is a subroutine called asynchronously by external hardware (usually an I/O device) during the execution of another application. The CPU halts execution of its current process by saving the system state and next instruction, and then jumps to the interrupt service routine, executes it, loads the saved system state and saved next instruction, and continues execution. Interrupts are good for handling infrequent events such as keyboard activity. Interrupts on this cpuModule are controlled by two Intel 8259-equivalent interrupt controllers containing 13 available interrupt request lines. What happens when an interrupt occurs? An IRQx pin on the PC/104 bus makes a low to high transition while the corresponding interrupt mask bit is unmasked and the PIC determines that the IRQ has priority, that is, the PIC interrupts the processor. The current code segment (CS), instruction pointer (IP), and flags are pushed onto the stack. The CPU then reads the 8-bit vector number from the PIC, and a new CS and IP are loaded from a vector—indicated by the vector number— from the interrupt vector table that typically exists in the lowest 1024 bytes of memory. The processor then begins executing instructions located at CS:IP. When the interrupt service routine is completed the CS, IP, and flags that were pushed onto the stack are popped from the stack into their appropriate registers and execution resumes from the point where it was interrupted. How long does it take to respond to an interrupt? A DOS system can respond to an interrupt between 6 and 15 μs. A Windows system can take a much longer time when a service routine has been installed by a device driver implemented as a DLL—from 250 to 1500 μs or longer. The time the CPU spends in the interrupt depends on the efficiency of the code in the ISR. These numbers are general guidelines and will fluctuate depending on operating system and version. Minimum time between two IRQ requests is 125 ns per ISA specification. Hardware Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer, the ISA bus has eight different interrupt request (IRQ) lines. On the ISA bus, a transition from low to high on one of these lines generates an interrupt request, which is handled by the PC’s interrupt controller. On the PCI bus, an interrupt request is level-triggered. The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and, if another interrupt is already in progress, it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done. This prioritizing allows an interrupt to be interrupted if the second request has a higher priority. The priority level is based on the number of the IRQ; IRQ0 has the highest priority, IRQ1 is second-highest, and so on through IRQ7, which has the lowest. Many of the IRQs are used by the standard system resources. Therefore, it is important to know which IRQ lines are available in your system for use by the cpuModule. The CME136686LX cpuModule supports the standard PC Interrupt Request Lines (IRQs) listed below. This table represents a default (or near default) cpuModule configuration. IRQs not in use by hardware on the cpuModule itself are available for use. WARNING Installing a peripheral that conflicts with the IRQs of the onboard hardware may prevent the system from functioning! BDM-610000065 Rev C Chapter 4: Using the cpuModule 87
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CME136686LX cpuModules User’s Man
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CME136686LX cpuModules www.rtd.com
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Chapter 1 Introduction Table of Con
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Status LEDs . . . . . . . . . . . .
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Chapter 1 Introduction This manual
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LVDS Panel (CN19) COM1 (CN8) Batter
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Cable Kits and Accessories For maxi
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- Easy to Use • Low Power Feature
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Block Diagram The next figure shows
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Electrical Characteristics The tabl
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2. Maximum DC undershoot below grou
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Chapter 2 Getting Started For many
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Table 5 CME136686LX Basic Connector
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Connecting to the PC/104 Bus The PC
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Chapter 3 Connecting the cpuModule
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Table 6 CME136686LX Basic Connector
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WARNING If you connect power incorr
Page 35 and 36: Keyboard A PS/2 compatible keyboard
Page 37 and 38: SVGA Video Connector (CN18) Table 1
Page 39 and 40: LVDS Flat Panel Video Connector (CN
Page 41 and 42: ATA/IDE Disk Chip Socket (U16) The
Page 43 and 44: Serial Port 1 (CN7) and Serial Port
Page 45 and 46: RS-422 and RS-485 Mode Pinout Table
Page 47 and 48: Table 25 COM A (RS-422/485) and COM
Page 49 and 50: multiPort Configured as a Parallel
Page 51 and 52: USB 2.0 Connector (CN17) Two USB 2.
Page 53 and 54: PC/104 Bus (CN1 and CN2) Connectors
Page 55 and 56: Table 33 PC/104 Bus Signals 1 (cont
Page 57 and 58: Chapter 4 Using the cpuModule This
Page 59 and 60: Main Menu Setup Fields The followin
Page 61 and 62: Memory Map The CME136686LX is a 32-
Page 63 and 64: Table 39 I/O Addresses Reserved for
Page 65 and 66: I/O Address Aliasing Traditionally,
Page 67 and 68: multiPort: Advanced Digital I/O Por
Page 69 and 70: Table 47 Interrupt Mask Enable 454h
Page 71 and 72: Status LEDs • Link: When Ethernet
Page 73 and 74: Legacy Mode IDE The onboard EIDE co
Page 75 and 76: Table 49 Real Time Clock Registers
Page 77 and 78: Watchdog Timer Control The cpuModul
Page 79 and 80: Thermal Management The cpuModule ha
Page 81 and 82: AT vs. ATX Power Supplies Both AT a
Page 83 and 84: EMI Management Electromagnetic inte
Page 85: Features and Settings That Can Affe
Page 89 and 90: Intel 8259 Programmable Interrupt C
Page 91 and 92: Appendix A Hardware Reference This
Page 93 and 94: Figure shows the jumper locations t
Page 95 and 96: Physical Dimensions Figure 7 shows
Page 97 and 98: Appendix B Troubleshooting Many pro
Page 99 and 100: Table 58 Troubleshooting (cont’d)
Page 101 and 102: Appendix C IDAN Dimensions and Pino
Page 103 and 104: IDAN Connectors 15-pin high-density
Page 105 and 106: Table 61 COM1/COM2 (RS-232) — 9-P
Page 107 and 108: Table 64 Panel — 20-Pin mini D Co
Page 109 and 110: Appendix D Additional Information A
Page 111 and 112: Appendix E Limited Warranty RTD Emb
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