Intel Server Board S3000AH - Viglen Download

Functional Architecture
Intel® Server Board S3000AH TPS
memory interface bandwidth and maximum memory configuration with a 72-bit wide memory
interface.
The MCH integrates the following main functions:
• An integrated high performance main memory subsystem
• A PCI Express* bus which provides an interface to the PCIexpress devices( Fully
compliant to the PCI Express* Base Specification, Rev 1.0a)
• A DMI which provides an interface to the Intel ® ICH7R
Other features provided by the MCH include the following:
• Full support of ECC on the processor bus
• Full support of Intel ® x4 Single Device Data Correction on the memory interface with x4
DIMMs
• Twelve deep in-order queue, two deep defer queue
• Full support of un-buffered DDR2 ECC DIMMs
• Support for 512MB, 1 GB and 2 GB DDR2 memory modules
• Memory scrubbing
3.2.1.2 Segment F PCIe* x8
The MCH PCIe* Lanes 0~7 provide a x8 PCIe connection directly to the MCH. This resource
can support x1, x4, x 8 PCIe add-in cards or through the I/O riser when using the Intel ® Adaptive
Slot.
Table 4. Segment F Connections
Lane
Device
Lane 0~7 Slot 6 or Super Slot (PCI Express* x8)
3.2.1.3 MCH Memory Sub-System Overview
The MCH supports a 72-bit wide memory sub-system that can support a maximum of 8 GB of
DDR2 memory using 2GB DIMMs. This configuration needs external registers for buffering the
memory address and control signals. The four chip selects are registered inside the MCH and
need no external registers for chip selects.
The memory interface runs at 533/667MT/s. The memory interface supports a 72-bit wide
memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256 MB,
512 MB, 1 GB, and 2 GB DRAM densities. The DDR DIMM interface supports single-bit error
correction, and multiple bit error detection.
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Revision 1.0