Intel Server Board S3000AH - Viglen Download

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Functional Architecture Intel® Server Board S3000AH TPS Table 8. Memory Bank Labels and DIMM Population Order Location DIMM Label Channel Population Order J8J1 (DIMM_1A) A 1 J8J2 (DIMM_2A) A 3 J9J1 (DIMM_1B) B 2 J9J2 (DIMM_2B) B 4 Figure 9. Memory Bank Label Definition 26 Revision 1.0
Intel® Server Board S3000AH TPS Functional Architecture Table 9. Characteristics of Dual/Single Channel Configuration with or without Dynamic Mode Throughput Level Configuration Characteristics Highest Dual channel with dynamic paging mode All DIMMs matched Lowest Dual channel without dynamic paging mode Single channel with dynamic paging mode Single channel without dynamic paging mode DIMMs matched from Channel A to Channel B DIMMs not matched within channels Single DIMM or DIMMs matched within a channel DIMMs not matched 3.3.2 Memory DIMM Support The board supports un-buffered (not registered) DDR2 533/667 ECC or Non-ECC DIMMs operating at 533/667MT/s. Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on this board. A list of qualified DIMMs is available at http://support.intel.com/support/motherboards/server/S3000AH. Note that all DIMMs are supported by design, but only fully qualified DIMMs will be supported on the board. The minimum supported DIMM size is 256 MB. Therefore, the minimum main memory configuration is 1 x 256 MB or 256 MB. The largest size DIMM supported is 2 GB and as such, the maximum main memory configuration is 8 GB implemented by 4 x 2 GB DIMMs. • Un-buffered DDR2 533/667 compliant, ECC x8 and Non-ECC x8 or x16 memory DIMMs are supported. • ECC single-bit errors (SBE) can be detected and corrected. Multiple-bit error (MBE) can only be detected. • The maximum memory capacity is 8 GB via four 2 GB DIMM modules. • The minimum memory capacity is 256 MB via a single 256 MB DIMM module. 3.4 I/O Sub-System 3.4.1 PCI Subsystem The primary I/O buses for the Intel ® Server Board S3000AH are five independent PCI bus segments providing PCI, PCIe* and PCI-X* resources (S3000AHLX SKU only). The PCI buses comply with the PCI Local Bus Specification, Rev 2.3. PCI Segments A, B and C and D are directed through the Intel ® ICH7R. PCI Segment E is independently configured to PXH-V that is through Intel ® ICH7R by PCI Express* x4 interface. PCI Segment F is directed through the MCH by PCIe x8 interface. The table below lists the characteristics of the three PCI bus segments. Revision 1.0 27
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Page 16 and 17: Introduction Intel® Server Board S
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