Intel Server Board S3000AH - Viglen Download
Intel Server Board S3000AH - Viglen Download
Intel Server Board S3000AH - Viglen Download
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Functional Architecture<br />
<strong>Intel</strong>® <strong>Server</strong> <strong>Board</strong> <strong>S3000AH</strong> TPS<br />
Table 6. Segment E Configuration IDs<br />
IDSEL Value<br />
Device<br />
18 PCI-X* Slot 5 (64bit/66-133MHz) (<strong>S3000AH</strong>LX SKU only)<br />
17 Super Slot 6 (64bit/66-100MHz) (Riser, <strong>S3000AH</strong>LX SKU only)<br />
3.2.2.1.2 Segment E Arbitration<br />
PXH-V supports two PCI masters: two PCI-X* slots or one riser slot. All PCI masters must<br />
arbitrate for PCI access using resources supplied by the PXH-V. The host bridge PCI interface<br />
(PXH-V) arbitration lines REQx* and GNTx* are a special case in that they are internal to the<br />
host bridge. The following table defines the arbitration connections.<br />
Table 7. Segment D Arbitration Connections<br />
Baseboard Signals<br />
Device<br />
PCIX REQ_N1/GNT_N1 PCI-X Slot 5 (64bit/66-133MHz) (<strong>S3000AH</strong>LX SKU only)<br />
PCIX REQ_N0/GNT_N0 Super Slot 6 (64bit/66-100MHz) (Riser, <strong>S3000AH</strong>LX SKU only)<br />
3.2.3 I/O Controller Hub<br />
3.2.3.1 <strong>Intel</strong> ® ICH7R: I/O Controller Hub 7R<br />
The <strong>Intel</strong> ® ICH7R controller has several components. It provides the interface for a 32-bit/33-<br />
MHz PCI bus. The <strong>Intel</strong> ® ICH7R can be both a master and a target on that PCI bus. The <strong>Intel</strong> ®<br />
ICH7R includes a USB 2.0 controller and an IDE controller. The <strong>Intel</strong> ® ICH7R is responsible for<br />
much of the power management functions with ACPI control registers built in. The <strong>Intel</strong> ® ICH7R<br />
also provides a number of General Purpose I/O (GPIO) pins and has the Low Pin Count (LPC)<br />
bus to support low speed Legacy I/O.<br />
The MCH and <strong>Intel</strong> ® ICH7R chips provide the pathway between the processor and the I/O<br />
systems. The MCH is responsible for accepting access requests from the host (processor) bus,<br />
and directing all I/O accesses to one of the PCI buses or Legacy I/O locations. If the cycle is<br />
directed to one of the PCIe* segments, the MCH communicates with the PCIe Devices (add-in<br />
card, on board devices) through the PCIe interface. If the cycle is directed to the <strong>Intel</strong> ® ICH7R,<br />
the cycle is output on the MCH’s DMI bus. All I/O for the board, including PCI and PCcompatible<br />
I/O, is directed through the MCH and then through the <strong>Intel</strong> ® ICH7R provided PCI<br />
buses.<br />
The <strong>Intel</strong> ® ICH7R is a multi-function device, housed in a 609-pin mBGA device. It provides the<br />
following:<br />
• A DMI bus<br />
• A PCI 32-bit/33 MHz interface<br />
• An IDE interface<br />
• An integrated Serial ATA Host controller<br />
22<br />
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