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Galileo OS SIS ICD.indd - GSA - Europa

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List of Tables<br />

Table 1. Carrier Frequency per Signal ........................................................................................................2<br />

Table 2. <strong>Galileo</strong> Signals Receiver Reference Bandwidths ..........................................................................3<br />

Table 3. Signal Description Parameters......................................................................................................4<br />

Table 4. E5 Chip Rates and Symbol Rates.................................................................................................5<br />

Table 5. AltBOC Subcarrier Coeffi cients .....................................................................................................6<br />

Table 6. Look-up Table for AltBOC Phase States .......................................................................................7<br />

Table 7. E6 Chip Rates and Symbol Rates.................................................................................................8<br />

Table 8. E1 SoL CBOC Chip- and Sub-carrier Rates .................................................................................9<br />

Table 9. E1 SoL Symbol Rates ...................................................................................................................9<br />

Table 10. Logic to Signal Level Assignment ...............................................................................................10<br />

Table 11. Received Minimum Power Levels on Ground .............................................................................10<br />

Table 12. Additional Losses due to Receiver Filtering ................................................................................ 11<br />

Table 13. Code Lengths ..............................................................................................................................12<br />

Table 14. E5 Primary Codes Specifi cations ................................................................................................14<br />

Table 15. Base Register 2 start Values and First Code Chip for E5a-I .......................................................15<br />

Table 16. Base Register 2 Start Values and First Code Chip for E5a-Q .....................................................16<br />

Table 17. Base Register 2 Start Values and First Code Chip for E5b-I ......................................................17<br />

Table 18. Base Register 2 Start Values and First Code Chip for E5b-Q .....................................................18<br />

Table 19. Secondary Code Sequences (Part 1) .........................................................................................20<br />

Table 20. Secondary Code Sequences (Part 2) .........................................................................................21<br />

Table 21. Secondary Code Assignment ......................................................................................................22<br />

Table 22. Allocation of E5a-I, E5a-Q, E5b-I and E5b-Q primary codes to SVIDs .......................................23<br />

Table 23. Allocation of L1-B and L1-C primary codes to SVIDs .................................................................24<br />

Table 24. Allocation of E5a-I, E5a-Q, E5b-I and E5b-Q secondary codes to SVIDs ..................................25<br />

Table 25. Allocation of L1-C secondary codes to SVIDs ............................................................................25<br />

Table 26. Message Allocation and General Data Content ..........................................................................26<br />

Table 27. Data Coding Parameters.............................................................................................................27<br />

Table 28. Interleaving Parameters ..............................................................................................................27<br />

Table 29. F/NAV Page Layout .....................................................................................................................28<br />

Table 30. F/NAV Frame Layout ...................................................................................................................31<br />

Table 31. Bits Allocation for F/NAV Page Type 1 ........................................................................................31<br />

Table 32. Bits Allocation for F/NAV Page Type 2 ........................................................................................31<br />

Table 33. Bits Allocation for F/NAV Page Type 3 ........................................................................................31<br />

Table 34. Bits Allocation for F/NAV Page Type 4 ........................................................................................32<br />

Table 35. Bits Allocation for F/NAV Page Type 5 ........................................................................................32<br />

Table 36. Bits Allocation for F/NAV Page Type 6 ........................................................................................32<br />

Table 37. Bits Allocation for F/NAV Dummy Page ......................................................................................32<br />

Table 38. I/NAV Page Part Layout ..............................................................................................................33<br />

Table 39. I/NAV Nominal Page with Bits Allocation .....................................................................................34<br />

Table 40. I/NAV Alert Page with Bits Allocation ...........................................................................................35<br />

Table 41. I/Nav Nominal Sub-Frame Structure ...........................................................................................36<br />

Table 42. I/NAV Sub-Frame Sequencing ....................................................................................................38<br />

Table 43. Bits Allocation for I/NAV Word Type 1 .........................................................................................38<br />

Table 44. Bits Allocation for I/NAV Word Type 2 .........................................................................................38<br />

Table 45. Bits Allocation for I/NAV Word Type 3 .........................................................................................39<br />

Table 46. Bits Allocation for I/NAV Word Type 4 .........................................................................................39<br />

Table 47. Bits Allocation for I/NAV Word Type 5 .........................................................................................39<br />

Table 48. Bits Allocation for I/NAV Word Type 6 .........................................................................................39<br />

Table 49. Bits Allocation for I/NAV Word Type 7 .........................................................................................39<br />

Table 50. Bits Allocation for I/NAV Word Type 8 .........................................................................................40<br />

© European Union 2010<br />

Document subject to terms of use and disclaimers p. ii-iii<br />

OD <strong>SIS</strong> <strong>ICD</strong>, Issue 1, February 2010<br />

ix

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