VS1003 Datasheet - VLSI Solution

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1.10 REF<strong>VS1003</strong>5 PACKAGES AND PIN DESCRIPTIONS5 Packages and Pin Descriptions5.1 PackagesBoth LPQFP-48 and BGA-49 are lead (Pb) free and also RoHS compliant packages. RoHSis a short name of Directive 2002/95/EC on the restriction of the use of certain hazardoussubstances in electrical and electronic equipment.5.1.1 LQFP-48148Figure 5: Pin Configuration, LQFP-48.LQFP-48 package dimensions are at http://www.vlsi.fi/ .5.1.2 BGA-49A1 BALL PAD CORNER1 2 3 4 5 6 7ABCDE0.80 TYP4.807.00FG1.10 REF0.80 TYP4.807.00TOP VIEWFigure 6: Pin Configuration, BGA-49.BGA-49 package dimensions are at http://www.vlsi.fi/ .Version: 1.06, 2012-03-16 12
<strong>VS1003</strong>5 PACKAGES AND PIN DESCRIPTIONS5.2 LQFP-48 and BGA-49 Pin DescriptionsPin NameLQFP-48PinBGA49BallPinTypeFunctionMICP 1 C3 AI Positive differential microphone input, self-biasingMICN 2 C2 AI Negative differential microphone input, self-biasingXRESET 3 B1 DI Active low asynchronous resetDGND0 4 D2 DGND Core & I/O groundCVDD0 5 C1 CPWR Core power supplyIOVDD0 6 D3 IOPWR I/O power supplyCVDD1 7 D1 CPWR Core power supplyDREQ 8 E2 DO Data request, input busGPIO2 / DCLK 1 9 E1 DIO General purpose IO 2 / serial input data bus clockGPIO3 / SDATA 1 10 F2 DIO General purpose IO 3 / serial data inputXDCS / BSYNC 1 13 E3 DI Data chip select / byte syncIOVDD1 14 F3 IOPWR I/O power supplyVCO 15 G2 DO For testing only (Clock VCO output)DGND1 16 F4 DGND Core & I/O groundXTALO 17 G3 AO Crystal outputXTALI 18 E4 AI Crystal inputIOVDD2 19 G4 IOPWR I/O power supplyIOVDD3 F5 IOPWR I/O power supplyDGND2 20 DGND Core & I/O groundDGND3 21 G5 DGND Core & I/O groundDGND4 22 F6 DGND Core & I/O groundXCS 23 G6 DI Chip select input (active low)CVDD2 24 G7 CPWR Core power supplyRX 26 E6 DI UART receive, connect to IOVDD if not usedTX 27 F7 DO UART transmitSCLK 28 D6 DI Clock for serial busSI 29 E7 DI Serial inputSO 30 D5 DO3 Serial outputCVDD3 31 D7 CPWR Core power supplyTEST 32 C6 DI Reserved for test, connect to IOVDDGPIO0 / SPIBOOT 33 C7 DIO General purpose IO 0 / SPIBOOT, use 100 kΩ pulldownresistor 2GPIO1 34 B6 DIO General purpose IO 1AGND0 37 C5 APWR Analog ground, low-noise referenceAVDD0 38 B5 APWR Analog power supplyRIGHT 39 A6 AO Right channel outputAGND1 40 B4 APWR Analog groundAGND2 41 A5 APWR Analog groundGBUF 42 C4 AO Common buffer for headphonesAVDD1 43 A4 APWR Analog power supplyRCAP 44 B3 AIO Filtering capacitance for referenceAVDD2 45 A3 APWR Analog power supplyLEFT 46 B2 AO Left channel outputAGND3 47 A2 APWR Analog groundLINEIN 48 A1 AI Line input1 First pin function is active in New Mode, latter in Compatibility Mode.2 Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.5 for details.Version: 1.06, 2012-03-16 13
Page 4 and 5: VS1003CONTENTS10.4 SCI Registers .
Page 6 and 7: VS10033 DEFINITIONS1 LicensesMPEG L
Page 8 and 9: VS10034 CHARACTERISTICS & SPECIFICA
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Page 14 and 15: VS10035 PACKAGES AND PIN DESCRIPTIO
Page 16 and 17: VS10037 SPI BUSES7 SPI Buses7.1 Gen
Page 18 and 19: VS10037 SPI BUSES7.4.3 SDI in VS100
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Page 24 and 25: VS10038 FUNCTIONAL DESCRIPTION8.2.2
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Page 40 and 41: VS10039 OPERATIONA way to see if yo
Page 42 and 43: VS10039 OPERATION9.5 SPI BootIf GPI
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Page 46 and 47: VS100310 VS1003 REGISTERSInstructio
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