VS1003 Datasheet - VLSI Solution

VS100310 VS1003 REGISTERS10.10 Watchdog v1.0 2002-08-26The watchdog consist of a watchdog counter and some logic. After reset, the watchdog isinactive. The counter reload value can be set by writing to WDOG_CONFIG. The watchdog isactivated by writing 0x4ea9 to register WDOG_RESET. Every time this is done, the watchdogcounter is reset. Every 65536’th clock cycle the counter is decremented by one. If the counterunderflows, it will activate vsdsp’s internal reset sequence.Thus, after the first 0x4ea9 write to WDOG_RESET, subsequent writes to the same registerwith the same value must be made no less than every 65536×WDOG_CONFIG clock cycles.Once started, the watchdog cannot be turned off. Also, a write to WDOG_CONFIG doesn’tchange the counter reload value.After watchdog has been activated, any read/write operation from/to WDOG_CONFIG or WDOG_DUMMYwill invalidate the next write operation to WDOG_RESET. This will prevent runaway loops fromresetting the counter, even if they do happen to write the correct number. Writing a wrong valueto WDOG_RESET will also invalidate the next write to WDOG_RESET.Reads from watchdog registers return undefined values.10.10.1 RegistersWatchdog, prefix WDOG_Reg Type Reset Abbrev Description0xC020 w 0 CONFIG Configuration0xC021 w 0 RESET Clock configuration0xC022 w 0 DUMMY[-] Dummy registerVersion: 1.06, 2012-03-16 50