VS1003 Datasheet - VLSI Solution

VS10038 FUNCTIONAL DESCRIPTION8.6.4 SCI_CLOCKF (RW)The operation of SCI_CLOCKF is different in VS1003 than in VS10x1 and VS1002.SCI_CLOCKF bitsName Bits DescriptionSC_MULT 15:13 Clock multiplierSC_ADD 12:11 Allowed multiplier additionSC_FREQ 10: 0 Clock frequencySC_MULT activates the built-in clock multiplier. This will multiply XTALI to create a higher CLKI.The values are as follows:SC_MULT MASK CLKI0 0x0000 XTALI1 0x2000 XTALI×1.52 0x4000 XTALI×2.03 0x6000 XTALI×2.54 0x8000 XTALI×3.05 0xa000 XTALI×3.56 0xc000 XTALI×4.07 0xe000 XTALI×4.5SC_ADD tells, how much the decoder firmware is allowed to add to the multiplier specified bySC_MULT if more cycles are temporarily needed to decode a WMA stream. The values are:SC_ADD MASK Multiplier addition0 0x0000 No modification is allowed1 0x0800 0.5×2 0x1000 1.0×3 0x1800 1.5×SC_FREQ is used to tell if the input clock XTALI is running at something else than 12.288 MHz.XTALI is set in 4 kHz steps. The formula for calculating the correct value for this register isXT ALI−80000004000(XTALI is in Hz).Note: The default value 0 is assumed to mean XTALI=12.288 MHz.Note: because maximum sample rate is< 12.288 MHz.XT ALI256, all sample rates are not available if XTALINote: Automatic clock change can only happen when decoding WMA files. Automatic clockchange is done one 0.5× at a time. This does not cause a drop to 1.0× clock and you canuse the same SCI and SDI clock throughout the WMA file. When decoding ends the defaultmultiplier is restored and can cause 1.0× clock to be used momentarily.Example: If SCI_CLOCKF is 0x9BE8, SC_MULT = 4, SC_ADD = 3 and SC_FREQ = 0x3E8 = 1000.This means that XTALI = 1000 × 4000 + 8000000 = 12 MHz. The clock multiplier is set to3.0×XTALI = 36 MHz, and the maximum allowed multiplier that the firmware may automaticallychoose to use is (3.0 + 1.5)×XTALI = 54 MHz.Version: 1.06, 2012-03-16 32