VS1003 Datasheet - VLSI Solution

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VS10038 FUNCTIONAL DESCRIPTION8.6.11 SCI_VOL (RW)SCI_VOL is a volume control for the player hardware. For each channel, a value in the range of0..254 may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps).The left channel value is then multiplied by 256 and the values are added. Thus, maximumvolume is 0 and total silence is 0xFEFE.Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256)+ 7 = 0x407. Note, that at startup volume is set to full volume. Resetting the software does notreset the volume setting.Note: Setting SCI_VOL to 0xFFFF will activate analog powerdown mode.8.6.12 SCI_AICTRL[x] (RW)SCI_AICTRL[x] registers ( x=[0 .. 3] ) can be used to access the user’s application program.Version: 1.06, 2012-03-16 36
VS10039 OPERATION9 Operation9.1 ClockingVS1003 operates on a single, nominally 12.288 MHz fundamental frequency master clock. Thisclock can be generated by external circuitry (connected to pin XTALI) or by the internal clockcrystal interface (pins XTALI and XTALO).9.2 Hardware ResetWhen the XRESET -signal is driven low, VS1003 is reset and all the control registers andinternal states are set to the initial values. XRESET-signal is asynchronous to any externalclock. The reset mode doubles as a full-powerdown mode, where both digital and analog partsof VS1003 are in minimum power consumption stage, and where clocks are stopped. AlsoXTALO is grounded.After a hardware reset (or at power-up) DREQ will stay down for at least 16600 clock cycles,which means an approximate 1.35 ms delay if VS1003 is run at 12.288 MHz. After this theuser should set such basic software registers as SCI_MODE, SCI_BASS, SCI_CLOCKF, andSCI_VOL before starting decoding. See section 8.6 for details.Internal clock can be multiplied with a PLL. Supported multipliers through the SCI_CLOCKFregister are 1.0 × . . . 4.5× the input clock. Reset value for Internal Clock Multiplier is 1.0×. Iftypical values are wanted, the Internal Clock Multiplier needs to be set to 3.0× after reset. Waituntil DREQ rises, then write value 0x9800 to SCI_CLOCKF (register 3). See section 8.6.4 fordetails.9.3 Software ResetIn some cases the decoder software has to be reset. This is done by activating bit 2 inSCI_MODE register (Chapter 8.6.1). Then wait for at least 2 µs, then look at DREQ. DREQwill stay down for at least 16600 clock cycles, which means an approximate 1.35 ms delay ifVS1003 is run at 12.288 MHz. After DREQ is up, you may continue playback as usual.If you want to make sure VS1003 doesn’t cut the ending of low-bitrate data streams and youwant to do a software reset, it is recommended to feed 2048 zeros (honoring DREQ) to the SDIbus after the file and before the reset. This is especially important for MIDI files, although youcan also use SCI_HDAT1 polling.If you want to interrupt the playing of a WAV, WMA, or MIDI file in the middle, set SM_OUTOFWAVin the mode register, and wait until SCI_HDAT1 is cleared (with a two-second timeout) beforecontinuing with a software reset. MP3 does not currently implement the SM_OUTOFWAV becauseit is a stream format, thus the timeout requirement.Version: 1.06, 2012-03-16 37
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