VS1003 Datasheet - VLSI Solution

VS10038 FUNCTIONAL DESCRIPTION8.5 Serial Control Interface (SCI)The serial control interface is compatible with the SPI bus specification. Data transfers arealways 16 bits. VS1003 is controlled by writing and reading the registers of the interface.The main controls of the control interface are:• control of the operation mode, clock, and builtin effects• access to status information and header data• access to encoded digital data• uploading user programs8.6 SCI RegistersSCI registers, prefix SCI_Reg Type Reset Time 1 Abbrev[bits] Description0x0 rw 0x800 70 CLKI 4 MODE Mode control0x1 rw 0x3C 3 40 CLKI STATUS Status of VS10030x2 rw 0 2100 CLKI BASS Built-in bass/treble enhancer0x3 rw 0 11000 XTALI 5 CLOCKF Clock freq + multiplier0x4 rw 0 40 CLKI DECODE_TIME Decode time in seconds0x5 rw 0 3200 CLKI AUDATA Misc. audio data0x6 rw 0 80 CLKI WRAM RAM write/read0x7 rw 0 80 CLKI WRAMADDR Base address for RAMwrite/read0x8 r 0 - HDAT0 Stream header data 00x9 r 0 - HDAT1 Stream header data 10xA rw 0 3200 CLKI 2 AIADDR Start address of application0xB rw 0 2100 CLKI VOL Volume control0xC rw 0 50 CLKI 2 AICTRL0 Application control register 00xD rw 0 50 CLKI 2 AICTRL1 Application control register 10xE rw 0 50 CLKI 2 AICTRL2 Application control register 20xF rw 0 50 CLKI 2 AICTRL3 Application control register 31 This is the worst-case time that DREQ stays low after writing to this register. The user maychoose to skip the DREQ check for those register writes that take less than 100 clock cycles toexecute.2 In addition, the cycles spent in the user application routine must be counted.3 Firmware changes the value of this register immediately to 0x38, and in less than 100 ms to0x30.4 When mode register write specifies a software reset the worst-case time is 16600 XTALIcycles.5 Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is nota good idea to send SCI or SDI bits while this register update is in progress.Note that if DREQ is low when an SCI write is done, DREQ also stays low after SCI writeprocessing.Version: 1.06, 2012-03-16 28