Introduction to Cadence - UPC

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Finally, alter pressing OK en in the analysis option tab, the simulation environment window should look like this:The simulation set-up is saved in a file named the ‘state’ of the simulation. There can be several simulation setupsfor the same schematic. This allows recovering the simulation environment set-up in subsequent sessions. Tosave the current set-up (‘state’) of the simulation environment follow the next steps:12 Introduction to schematic capture and simulation using Cadence DFW-II
Session -> Save State…The state name chain be choosen arbirtraryly but it is recommended to use meaningfull names. The states arestored in a hiden subdirectory named .artist_states, in the user home diretory, independently of theDFWII working directory.2.5.4 Run the simulation:Once the various simulation options have been selected, the simulation can be started in the following way, fromthe simulation environment menu: Simulation -> Run (or by clicking the green light button in the toolbar )A new text window pops-up showing simulation messages with information about the circuit and the simulationsteps. The simulation is finished if yu can see at the end the total time required for de analysis.2.5.5 Simulation results analysis:After the simulation ends, the results are stored in files and subdirectories under the simulation directoryspecified during the set-up step. We are interested in the open-loop gain and the phase response. We also want toobtain the bandwidth and the phase margin. These quantities are calculated from the simulation results. Thecalculator tool will be used for this purpose. From the simulation environment window the calculator tool is runin the following way:Tools -> CalculatorThe calculator operates on current and voltage waveforms saved in the simulation results file after the simulation.These waveforms are selected by clicking at the corresponding nodes or terminals in the schematic circuit.Therefore, we need the Virtuoso Schematic Editor window opened simultaneously with the simulationenvironment. Always look at the bottom part of the schematic window to check if there is some node selectioncommand running and waiting for a response. To cancel these commands just press ESC key. The calculator usesRCL notation and stores intermediate results in a stack. To visualize this stack just press the button DisplayStack on the calculator window. Now let’s practice with the calculator tool.Open loop gain measurement- Click vf (this means voltage against frequency, the result of AC analysis)- Select in the schematic the following nodes in the order listed: out, inp, inn, you should not press enterafter each selection (the calculator window should look like this):13
Page 2 and 3: Attach to an existing technolgy fil
Page 4 and 5: There are Views that contain the in
Page 6 and 7: simulators. The signals that go fro
Page 8 and 9: Comp Library Cell View Parameter Co
Page 10 and 11: In the new Virtuoso Schematic Edito
Page 14 and 15: - In the calculator press first ‘
Page 16 and 17: 2.5.6 Saving the results:The simula
Page 18 and 19: output OUT;input INN,INP,VDD,VSS;el
Page 20 and 21: Since the VerilogA model was parame
Page 22 and 23: 3.2.5 Circuit level and AHDL behavi

Introduction to Cadence - UPC

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