Introduction to Cadence - UPC

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- In the calculator press first ‘-‘ and next ‘/’. Finally press the dB20 button. The window should looklike these after the previous sequence of operations:- The button plot draws the calculated expression, if it is a waveform, that is found at the first level ofthe stack (note that if the expression results is a number, the button print should be used instead of plotto print the numeric result in a new window that will pop-up).14 Introduction to schematic capture and simulation using Cadence DFW-II
If you don’t get this exactly plot, go to the op_amp and op_amp_test schematics and pay attention if you havemade any mistake drawing the circuits.Phase noise responseProceed in a similar way as before to get the following expression in the first level of the calculatorstack:Press the plot button to draw the new curve. Now the Waveform window shows two overlaped curves.To place each curve in a different panel use the following option of the Waveform window menu:- Axes->To StripTittles and labes can be added from the annotaion menu (see next page for an example):- Annotation->Title-3dB Cut-off frequency, Phase marginThese two measurements are numeric results, not waveforms. They can be calculated with the followingexpressions using the calculator:bandwidth(VF(“/out”)/(VF(“/inp”)-VF(“/inn”)),3,”low”)The result can be visualized by pressing the PRINT button. The -3db cut-off frequency should be 15.9Hz. The phase margin is calculated with the following expression:phaseMargin(VF(“/out”)/(VF(“/inp”)-VF(“/inn”)))It is the difference between the phase 180º and the phase equivalent to the frequency when the gain isunity. It should result in approximately 50º.This figure shows the final aspect that should have the Waveform window after plotting the results.15
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Page 6 and 7: simulators. The signals that go fro
Page 8 and 9: Comp Library Cell View Parameter Co
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Page 16 and 17: 2.5.6 Saving the results:The simula
Page 18 and 19: output OUT;input INN,INP,VDD,VSS;el
Page 20 and 21: Since the VerilogA model was parame
Page 22 and 23: 3.2.5 Circuit level and AHDL behavi

Introduction to Cadence - UPC

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