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# Introduction to Cadence - UPC

## Since the VerilogA model

Since the VerilogA model was parameterised, you have to assign the correct values to the bandwith and gainparameters. You can obtain these numbers from the simulation done at transitor level in the previos section: the -3dB cut-off frequency (15.9 Hz) and the gain in dB (105.5 dB). These parameters are defined for the op_amp cellinstante container in the op_amp_test testbench cell. This can be done as follows:In the Virtuoso Schematic Editor window (schematic view of op_amp_test cell): Select the op_amp symbol Edit->Properties->Objects…IN the form that pops-up, press the item list named Use Tools Filter20 Introduction to schematic capture and simulation using Cadence DFW-II

Fill in the model parameters as shown in the figure below:Finally, ckeck and save the changes done in the op_amp_test schematic.Design->Check and Save3.2.4 Simulation and resultsYou have to follow the same steps of sub sections 2.5.4 y 2.5.5. After the simulation ends you have to plot thephase response and open-loop gain. They should look like the following figure (next page):Now, the bandwidht and phase margin measurments should be, approximatelly, 16 Hz y 90 degrees, respectively(the large difference in the latter is due to the first order RC model used that has a sinble pole). Thesemeasurments are obtained using the following expressions in the calculator:bandwidth(VF(“/out”)/(VF(“/inp”)-VF(“/inn”)),3,”low”)phaseMargin(VF(“/out”)/(VF(“/inp”)-VF(“/inn”)))21

1. Introduction - UPC
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