Single-Chip Low Cost Low Power RF-Transceiver (Rev. B

CC2500Figure 7: Configuration Register Write and Read OperationsParameter Description Min Max Unitsf SCLKSCLK frequency100 ns delay inserted between address byte and data byte (single access), or betweenaddress and data, and between each data byte (burst access).SCLK frequency, single accessNo delay between address and data byteSCLK frequency, burst accessNo delay between address and data byte, or between data bytes- 10 MHz9 MHz6.5 MHzt sp,pd CSn low to positive edge on SCLK, in power-down mode 150 µst sp CSn low to positive edge on SCLK, in active mode 20 - nst ch Clock high 50 - nst cl Clock low 50 - nst rise Clock rise time - 5 nst fall Clock fall time - 5 nst sdSetup data (negative SCLK edge) topositive edge on SCLK(t sd applies between address and data bytes, andbetween data bytes)Single access 55 - nsBurst access 76 - nst hd Hold data after positive edge on SCLK 20 - nst ns Negative edge on SCLK to CSn high 20 - nsTable 16: SPI Interface Timing RequirementsNote: The minimum t sp,pd figure in Table 16 can be used in cases where the user does not read theCHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-downdepends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillatorstart-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK.10.1 Chip Status ByteWhen the header byte, data byte or, commandstrobe is sent on the SPI interface, the chipstatus byte is sent by the CC2500 on the SOpin. The status byte contains key statussignals, useful for the MCU. The first bit, s7, isthe CHIP_RDYn signal; this signal must go lowbefore the first positive edge of SCLK. TheCHIP_RDYn signal indicates that the crystal isrunning.Bits 6, 5, and 4 comprise the STATE value.This value reflects the state of the chip. TheXOSC and power to the digital core is on inthe IDLE state, but all other modules are inpower down. The frequency and channelSWRS040B Page 23 of 92