Single-Chip Low Cost Low Power RF-Transceiver (Rev. B

CC250036 General Information36.1 Document HistoryRevision Date Description/ChangesSWRS040B 2007-05-09 kbps replaced by kBaud throughout the document.Some of the sections has been re-written to be easier to read without having any new info added.Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V.FSK changed to 2-FSK throughout the document.Updates to the Abbreviation table.Updates to the Electrical Specifications section. Added ACP, OBW and blocking performance.Maximum output power changed from 0 dBm to +1 dBm.Added information about reduced link performance at n/2·crystal frequency.Added info about RX and TX latency in serial mode.Changes to the maximum RC oscillator frequency accuracy after calibration.Added info about default values after reset versus optimum register settings in the ConfigurationSoftware section.Changes to the SPI Interface Timing Requirements. Info added about t sp,pdThe following figures has been changed: Configuration Registers Write and Read Operations,SRES Command Strobe, and Register Access Types.In the Register Access section, the address range is changed.Changes to PATABLE Access section.In the Packet Format section, preamble pattern is changed to 10101010 and info about bug relatedto turning off the transmitter in infinite packet length mode is added.Added info to the Frequency Offset Compensation section.Added info about the initial value of the PN9 sequence in the Data Whitening section.Added info about TX FIFO underflow state in the Packet Handling in Transmit Mode section.Added section Packet Handling in Firmware.In the PQT section a change is made as to how much the counter decreases.The RSSI value is in dBm and not dB.The whole CS Absolute Threshold section has been re-written and the equation calculating thethreshold has been removed.Added info in the CCA section on what happens if the channel is not clear.Added info to the LQI section for better understanding.Removed all references to the voltage regulator in relation with the CHP_RDYn signal, as thissignal is only related to the crystal.Removed references to the voltage regulator in the figures: Power-On Reset and Power-On Resetwith SRES. Changes to the SI line in the Power-On Reset with SRES figure.Added info on the three automatic calibration options.Added info about minimum sleep time and references to App. Note 047 together with info aboutcalibration of the RC oscillator.The figure Event 0 and Event 1 Relationship is changed for better readability.Info added to the RC Oscillator and Timing section related to reduced calibration time.The Output Power Programming section has been changed. Only 1 PATABLE entry used for 2-FSK/GFSK/MSK and 2 PATABLE entries used for OOK. Added info on about PATABLE whenentering SLEEP mode. New PA_POWER and PATABLE figure.Added section on PCB Layout Recommendations.In section General Purpose / Test Output Control Pins: Added info on GDO pins in SLEEP state.Asynchronous transparent mode is called asynchronous serial mode throughout the document.Removed comments about having to use NRZ coding in synchronous serial mode. Added info thatManschester encoding cannot be used in this mode.Changed number of commands strobes from 14 to 13.Added two new registers; RCCTRL1_STATUS and RCCTRL0_STATUSChanged field name and/or description of the following registers:MCSM2, MCSM0, WORCTRL, FSCAL3, FSCAL2, FSCAL1, TEST2, TEST1 and TEST0.Added references.SWRS040B Page 89 of 92