Single-Chip Low Cost Low Power RF-Transceiver (Rev. B

CC2500by the radio hardware (e.g. MARCSTATE orTXBYTES), there is a small, but finite,probability that a single read from the registeris being corrupt. As an example, theprobability of any single read from TXBYTESbeing corrupt, assuming the maximum datarate is used, is approximately 80 ppm. Refer tothe CC2500 Errata Notes [1] for more details.10.4 Command StrobesCommand strobes may be viewed as singlebyte instructions to CC2500. By addressing acommand strobe register, internal sequenceswill be started. These commands are used todisable the crystal oscillator, enable receivemode, enable wake-on-radio etc. The 13command strobes are listed in Table 34 onpage 58.The command strobe registers are accessedby transferring a single header byte (no data isbeing transferred). That is, only the R/W bit,the burst access bit (set to 0), and the sixaddress bits (in the range 0x30 through 0x3D)are written. TheR/W bit canbe either one or zero and will determine howthe FIFO_BYTES_AVAILABLE field in thestatus byte should be interpreted.When writing command strobes, the statusbyte is sent on the SO pin.A command strobe may be followed by anyother SPI access without pulling CSn high.However, if an SRES strobe is being issued,one will have to wait for SO to go low againbefore the next header byte can be issued asshown in Figure 8. The command strobes areexecuted immediately, with the exception ofthe SPWD and the SXOFF strobes that areexecuted when CSn goes high.The TX FIFO is write-only, while the RX FIFOis read-only.The burst bit is used to determine if the FIFOaccess is a single byte access or a burstaccess. The single byte access methodexpects a header byte with the burst bit set tozero and one data byte. After the data byte anew header byte is expected; hence, CSn canremain low. The burst access method expectsone header byte and then consecutive databytes until terminating the access by settingCSn high.The following header bytes access the FIFOs:• 0x3F: Single byte access to TX FIFO• 0x7F: Burst access to TX FIFO• 0xBF: Single byte access to RX FIFO• 0xFF: Burst access to RX FIFOWhen writing to the TX FIFO, the status byte(see Section 10.1) is output for each new databyte on SO, as shown in Figure 7. This statusbyte can be used to detect TX FIFO underflowwhile writing data to the TX FIFO. Note thatthe status byte contains the number of bytesfree before writing the byte in progress to theTX FIFO. When the last byte that fits in the TXFIFO is transmitted on SI, the status bytereceived concurrently on SO will indicate thatone byte is free in the TX FIFO.The TX FIFO may be flushed by issuing aSFTX command strobe. Similarly, a SFRXcommand strobe will flush the RX FIFO. ASFTX or SFRX command strobe can only beissued in the IDLE, TXFIFO_UNDERLOW orRXFIFO_OVERFLOW states. Both FIFOs areflushed when going to the SLEEP state.Figure 9 gives a brief overview of differentregister access types possible.Figure 8: SRES Command Strobe10.5 FIFO AccessThe 64-byte TX FIFO and the 64-byte RXFIFO are accessed through the 0x3F address.When the R/W bit is zero, the TX FIFO isaccessed, and the RX FIFO is accessed whenthe R/W bit is one.10.6 PATABLE AccessThe 0x3E address is used to access thePATABLE, which is used for selecting PApower control settings. The PATABLE is an 8-byte table, but not all entries into this table areused. The entries to use are selected by the 3-bit value FREND0.PA_POWER.• When using 2-FSK, GFSK, or MSKmodulation only the first entry into thistable is used (index 0).SWRS040B Page 25 of 92