Single-Chip Low Cost Low Power RF-Transceiver (Rev. B

CC250019.7 RX Termination TimerCC2500 has optional functions for automatictermination of RX after a programmable time.The main use for this functionality is wake-onradio(WOR), but it may be useful for otherapplications. The termination timer starts whenin RX state. The timeout is programmable withthe MCSM2.RX_TIME setting. When the timerexpires, the radio controller will check thecondition for staying in RX; if the condition isnot met, RX will terminate.The programmable conditions are:• MCSM2.RX_TIME_QUAL=0: Continuereceive if sync word has been found• MCSM2.RX_TIME_QUAL=1: Continuereceive if sync word has been found orpreamble quality is above threshold (PQT)If the system can expect the transmission tohave started when enabling the receiver, theMCSM2.RX_TIME_RSSI function can be used.The radio controller will then terminate RX ifthe first valid carrier sense sample indicatesno carrier (RSSI below threshold). See Section17.4 on page 36 for details on Carrier Sense.For OOK modulation, lack of carrier sense isonly considered valid after eight symbolperiods. Thus, the MCSM2.RX_TIME_RSSIfunction can be used in OOK mode when thedistance between “1” symbols is 8 or less.If RX terminates due to no carrier sense whenthe MCSM2.RX_TIME_RSSI function is used,or if no sync word was found when using theMCSM2.RX_TIME timeout function, the chipwill always go back to IDLE if WOR is disabledand back to SLEEP if WOR is enabled.Otherwise, the MCSM1.RXOFF_MODE settingdetermines the state to go to when RX ends.This means that the chip will not automaticallygo back to SLEEP once a sync word has beenreceived. It is therefore recommended toalways wake up the microcontroller on syncword detection when using WOR mode. Thiscan be done by selecting output signal 6 (seeTable 33 on page 54) on one of theprogrammable GDO output pins, andprogramming the microcontroller to wake upon an edge-triggered interrupt from this GDOpin.20 Data FIFOThe CC2500 contains two 64 byte FIFOs, onefor received data and one for data to betransmitted. The SPI interface is used to readfrom the RX FIFO and write to the TX FIFO.Section 10.5 contains details on the SPI FIFOaccess. The FIFO controller will detectoverflow in the RX FIFO and underflow in theTX FIFO.When writing to the TX FIFO it is theresponsibility of the MCU to avoid TX FIFOoverflow. A TX FIFO overflow will result in anerror in the TX FIFO content.Likewise, when reading the RX FIFO the MCUmust avoid reading the RX FIFO past itsempty value, since an RX FIFO underflow willresult in an error in the data read out of the RXFIFO.The chip status byte that is available on the SOpin while transferring the SPI header containsthe fill grade of the RX FIFO if the access is aread operation and the fill grade of the TXFIFO if the access is a write operation. Section10.1 on page 23 contains more details on this.The number of bytes in the RX FIFO and TXFIFO can also be read from the statusregisters RXBYTES.NUM_RXBYTES andTXBYTES.NUM_TXBYTES respectively. If areceived data byte is written to the RX FIFO atthe exact same time as the last byte in the RXFIFO is read over the SPI interface, the RXFIFO pointer is not properly updated and thelast read byte is duplicated. To avoid thisproblem one should never empty the RX FIFObefore the last byte of the packet is received.For packet lengths less than 64 bytes it isrecommended to wait until the completepacket has been received before reading it outof the RX FIFO.If the packet length is larger than 64 bytes theMCU must determine how many bytes can beread from the RX FIFO(RXBYTES.NUM_RXBYTES-1) and the followingsoftware routine can be used:SWRS040B Page 44 of 92