Single-Chip Low Cost Low Power RF-Transceiver (Rev. B

CC2500options. Refer also to the CC2500 Errata Notes[1].15.4.1 PKTCTRL0.CC2400_EN=0If PKTCTRL0.CC2400_EN=0 it is possible toread back the CRC status in 2 different ways:1) Set PKTCTRL1.APPEND_STATUS=1 andread the CRC_OK flag in the MSB of thesecond byte appended to the RX FIFO afterthe packet data. This requires double bufferingof the packet, i.e. the entire packet content ofthe RX FIFO must be completely read outbefore it is possible to check whether the CRCindication is OK or not.2) To avoid reading the entire RX FIFO,another solution is to use thePKTCTRL1.CRC_AUTOFLUSH feature. If thisfeature is enabled, the entire RX FIFO will beflushed if the CRC check fails. IfGDOx_CFG=0x06 the GDOx pin will be assertedwhen a sync word is found. The GDOx pin willbe de-asserted at the end of the packet. Whenthe latter occurs the MCU should read thenumber of bytes in the RX FIFO from theRXBYTES.NUM_RXBYTES status register. IfRXBYTES.NUM_RXBYTES=0 the CRC checkfailed and the FIFO is flushed. IfRXBYTES.NUM_RXBYTES>0 the CRC checkwas OK and data can be read out of the FIFO.15.4.2 PKTCTRL0.CC2400_EN=1If PKTCTRL0.CC2400_EN=1 the CRC can bechecked as outlined in 1) in Section 15.4.1 aswell as by reading the CRC_OK flag availablein the PKTSTATUS[7] register, in the LQI[7]status register or from one of the GDO pins ifGDOx_CFG is 0x07 or 0x15.The PKTCTRL1.CRC_AUTOFLUSH or datawhitening cannot be used whenPKTCTRL0.CC2400_EN=1.15.5 Packet Handling in Transmit ModeThe payload that is to be transmitted must bewritten into the TX FIFO. The first byte writtenmust be the length byte when variable packetlength is enabled. The length byte has a valueequal to the payload of the packet (includingthe optional address byte). If addressrecognition is enabled on the receiver, thesecond byte written to the TX FIFO must bethe address byte. If fixed packet length isenabled, then the first byte written to the TXFIFO should be the address (if the receiveruses address recognition).The modulator will first send the programmednumber of preamble bytes. If data is availablein the TX FIFO, the modulator will send thetwo-byte (optionally 4-byte) sync word andthen the payload in the TX FIFO. If CRC isenabled, the checksum is calculated over allthe data pulled from the TX FIFO and theresult is sent as two extra bytes following thepayload data. If the TX FIFO runs emptybefore the complete packet has beentransmitted, the radio will enterTXFIFO_UNDERFLOW state. The only way toexit this state is by issuing an SFTX strobe.Writing to the TX FIFO after it has underflowedwill not restart TX mode.If whitening is enabled, everything followingthe sync words will be whitened. This is donebefore the optional FEC/Interleaver stage.Whitening is enabled by settingPKTCTRL0.WHITE_DATA=1.If FEC/Interleaving is enabled, everythingfollowing the sync words will be scrambled bythe interleaver and FEC encoded before beingmodulated. FEC is enabled by settingMDMCFG1.FEC_EN=1.15.6 Packet Handling in Receive ModeIn receive mode, the demodulator and packethandler will search for a valid preamble andthe sync word. When found, the demodulatorhas obtained both bit and byte synchronismand will receive the first payload byte.If FEC/Interleaving is enabled, the FECdecoder will start to decode the first payloadbyte. The interleaver will de-scramble the bitsbefore any other processing is done to thedata.If whitening is enabled, the data will be dewhitenedat this stage.When variable packet length mode is enabled,the first byte is the length byte. The packethandler stores this value as the packet lengthand receives the number of bytes indicated bythe length byte. If fixed packet length mode isused, the packet handler will accept theprogrammed number of bytes.Next, the packet handler optionally checks theaddress and only continues the reception if theaddress matches. If automatic CRC check isenabled, the packet handler computes CRCand matches it with the appended CRCchecksum.At the end of the payload, the packet handlerwill optionally write two extra packet statusSWRS040B Page 33 of 92