Intel(R) 80219 General Purpose PCI Processor Evaluation Platform ...

Intel® IQ80219 General Purpose PCI Processor Evaluation PlatformHardware Reference Section3.10.4 Jumper SummaryTable 31.Jumper SummaryJumper Association Description Factory DefaultJ1G2 PPCI-X Reset Can isolated the PCI-X reset from getting to the board. 2-3J3E1 SPCI-X Clock Enables spread-spectrum on the SPCI-X clock. 2-3J3G1 PCI-X Bridge Enables Bridge access from the SPCI-X side. 2-3J9E1 PCI-X Bridge Enables Base Address Register (BAR). 2-3J9F1PCI-X Bridge3.10.5 Connector SummaryAllows user to control initialization sequence on thebridge.2-3Table 32.Connector SummaryConnectorDescriptionJ1F1 RJ45 Network Connector for GbE NICJ1G1 RJ11 Serial Port Connector for UARTJ7A1 20-Pin JTAG Debug ConnectorJ1C1 Logic analyzer Mictor Connector for SPCI-X BusJ2C1 Logic analyzer Mictor Connector for SPCI-X BusJ3C1 Logic analyzer Mictor Connector for SPCI-X BusJ2F1 Logic analyzer Mictor Connector for 80219 Peripheral BusJ3F2 Logic analyzer Mictor Connector for 80219 Peripheral BusJ3F1 General Purpose I/O (GPIO) Header – GPIO 0-2J1A1 Secondary PCI-X Expansion SlotJ1B1 Secondary PCI-X Expansion Slot – Not PopulatedJ2H1 Primary PCI/PCI-X Edge ConnectorJ6G1 DDR DIMM ConnectorJ8H1 Connector for Battery3.10.6 General Purpose Input/Output HeaderThe board has three programmable general-purpose I/O pins (GPIO 0-3 on the 80321). These pins areconnected to a 6-pin, 2.54 mm (0.100") header (connector J3F1).Table 33.GPIO Header (J3F1) DefinitionPin Signal Pin Signal1 GPIO0 4 GND2 GPIO1 5 GND3 GPIO2 6 GNDBoard Manual 55