Intel(R) 80219 General Purpose PCI Processor Evaluation Platform ...
Intel(R) 80219 General Purpose PCI Processor Evaluation Platform ...
Intel(R) 80219 General Purpose PCI Processor Evaluation Platform ...
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<strong>Intel</strong>® IQ<strong>80219</strong> <strong>General</strong> <strong>Purpose</strong> <strong>PCI</strong> <strong>Processor</strong> <strong>Evaluation</strong> <strong>Platform</strong>Hardware Reference Section3.10.9.5 Switch S8E1- 2Turn On to enable on-board Gigabit Ethernet, otherwise Off for better <strong>PCI</strong>-X loading/performance.Table 47.Table 48.Switch S8E1 - 2: DescriptionsSwitch Association Description Factory DefaultS8E1-2S<strong>PCI</strong>-X BusSwitch S8E1 - 2: Settings and Operation ModeS8E1-2OffOnQSWITCHEN: Quick-Switch to make GbE NIC visibleon the S<strong>PCI</strong>-X bus.Operation Mode82544EI Isolated from secondary <strong>PCI</strong>-X bus.82544EI Included on as a device on the secondary <strong>PCI</strong>-X bus.On3.10.9.6 Switch S8E1- 3Close to enable bridge to be the arbiter.Table 49.Table 50.Switch S8E1 - 3: DescriptionsSwitch Association Description Factory DefaultS8E1-3 <strong>PCI</strong>-X Bridge S_INT_ARB_EN: Internal bridge arbiter operation. OnSwitch S8E1 - 3: Settings and Operation ModeS8E1-3Operation ModeOff Disable internal bridge arbiter, use external arbiter.On Use internal arbiter.3.10.9.7 Switch S8E1- 4Used to choose between 100 MHz and 133 MHz maximum operating frequency on the secondaryinterface when in the <strong>PCI</strong>-X mode. It has no meaning in the <strong>PCI</strong> mode.When the bridge initially samples a b’1’ value on the S_<strong>PCI</strong>XCAP input, then all clients on the busare capable of <strong>PCI</strong>-X 133 operation. The bridge then samples the S_SEL100 input to distinguishbetween the 66-100 MHz and the 100-133 MHz clock frequency ranges. When it detects a b’1’ valueon the S_SEL100 input, the bus is initialized with the <strong>PCI</strong>-X 100 initialization pattern. When thevalue is b’0’, the <strong>PCI</strong>-X 133 initialization pattern is used. These two ranges allow adjustment of theclock frequency to account for bus loading conditions.Since the internal PLL is bypassed in the <strong>PCI</strong> mode and the S_CLK input is used directly, the IBM133 <strong>PCI</strong>-X Bridge R2.0 has no need to distinguish between the <strong>PCI</strong> 66 and <strong>PCI</strong> 33 modes. Thereforethe bridge does not have an I/O pin for the M66EN signal on its secondary interface.Table 51.Table 52.Switch S8E1 - 4: DescriptionsSwitch Association Description Factory DefaultS8E1-4 <strong>PCI</strong>-X Bridge S_SEL100: S<strong>PCI</strong>-X max operation frequency indictor. OffSwitch S8E1 - 4: Settings and Operation ModeS8E1-4Operation ModeOff 1: 100 MHz.On 0: 133 MHz.60 Board Manual
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