"Linear Equation Solver using CMOS Technology" - Microelectronic ...

3.1.2. Revised DesignAs mentioned before, solver hardware is implemented in both VHDL (Appendix A2.2) and Cadenceenvironment. As shown in Figure 10, the basic building blocks are INV (Appendix A1.1), NAND(Appendix A1.2), XOR (Appendix A1.3), DLATCH (Appendix A1.4) and DFF (Appendix A1.5)cells. Here DFFs are inserted in order to break the feedback loops and prevent possible oscillations.The input buffers (Appendix A1.6) in Figure 11 are inserted for simulation purposes. Since testbenches are coded in VHDL (Appendix 2.2.2) and then applied to the Spectre, they are used tostimulate real input signal behavior with finite rise and fall times unlike the ideal ones.21