"Linear Equation Solver using CMOS Technology" - Microelectronic ...

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Figure 24. CADENCE Output waveforms_3 for the Final Solver Design (4 unknowns) - 8 inputsFigure 25. CADENCE Output waveforms_4 for the Final Solver Design (4 unknowns) - 25 inputs34
Figure 26. CADENCE Output waveforms_5 for the Final Solver Design (4 unknowns) - 30 inputs4.2. Digital Linear Equation Solver with 8 unknowns4.2.1. Final DesignFirst the circuit is simulated with the random inputs generated in MATLAB (Appendix 3.2) and noclock allocation is performed. Exactly the same logic is applied to the clocks as in chapter 4.1.2 and4.1.3 . They are generated in such a way that no clock is the integer multiple of the others. A defaultordering is selected and clocks are defined as 6 ns, 8 ns, 10 ns, 12 ns, 14 ns, 16 ns, 18 ns, 20 ns eachhaving their half of the period pulse width (Appendix A1.7.3), for the first DFF, second DFF, ... , forthe last DFF, respectively. The simulation setup is provided in Appendix A1.7.3.In addition, the random inputs are simulated with a transient simulation time of 5 us for each, since itis expected to be enough according to the simulations for the solver design with 4 unknowns. As thesimulation results reveal (Figure 27 - 32), for some input cases the circuit fails, and numericaloscillations are observed (Figure 30 - for the first two inputs). Analyzing the problematic inputs pointsout the numerical oscillations as the cause of circuit failure, not the insufficient transient simulationtime for each input (5 us).35
Page 2: AcknowledgementsI would like to tha
Page 5 and 6: A1.3. XOR Cell ....................
Page 7 and 8: Figure 44. Schematic of DFF gate ..
Page 9 and 10: Figure 2. Schematic of three LSFRs
Page 11 and 12: 2.1. Digital Linear Equation Solver
Page 13 and 14: 2.1.2. Revised DesignIn order to pr
Page 15 and 16: 2.1.3. Final DesignThe timing of th
Page 17 and 18: Figure 7. Schematic of the Final So
Page 19 and 20: After verifying the correct operati
Page 21 and 22: 3.1.2. Revised DesignAs mentioned b
Page 23 and 24: Figure 11. CADENCE Schematic of Rev
Page 25 and 26: Figure 12. CADENCE Schematic of the
Page 27 and 28: 4 Implementation Results4.1. Digita
Page 29 and 30: Figure 15. MODELSIM Output waveform
Page 31 and 32: Figure 19. CADENCE Output waveforms
Page 33: Figure 22. CADENCE Output waveforms
Page 37 and 38: Figure 28. CADENCE Output waveforms
Page 39 and 40: Figure 32. Output waveforms_6 for t
Page 41 and 42: Figure 36. Output waveforms_8 for t
Page 43 and 44: 5 Further Improvements and Comments
Page 45 and 46: 7 References1 - "Encryption" , Data
Page 47 and 48: A1.2. AND CellFigure 40. Schematic
Page 49 and 50: A1.4. DLATCH CellFigure 43. Schemat
Page 51 and 52: A1.6. Input BuffersFigure 45. Schem
Page 53 and 54: A1.7.2. Simulation Setup for the Re
Page 55 and 56: A2 VHDL CodesA2.1.Initial Solver (4
Page 57 and 58: Xout (2)
Page 59 and 60: A2.2.2.GenSolver4_tb.vhdAs mentione
Page 61 and 62: endcountfclose(fid);endelsextxt=[xt
Page 63: if(K==N) %if you cannot find a 1 in

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