"Linear Equation Solver using CMOS Technology" - Microelectronic ...

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Figure 17. CADENCE Output waveforms_1 for the Revised Solver Design (4 unknowns) - 7 inputsFigure 18. CADENCE Output waveforms_2 for the Revised Solver Design (4 unknowns) - 5 inputs30
Figure 19. CADENCE Output waveforms_3 for the Revised Solver Design (4 unknowns) - 8 inputs4.1.3. Final DesignExactly the same simulations are performed on the final solver design. All possible inputs aresimulated in MODELSIM and the correct functionality of the design is verified. The circuit has noassertion misses out of 27008 applied inputs (Figure 21). In addition, exactly the same clocks are usedas in the revised design. The simulation results are provided in Figure 20.Next, the transistor level simulations are performed for a detailed analysis. The simulation setup forthe final solver design is provided in Appendix A.1.7.2. A binary2decimal converter is added forfacilitating the analysis of the outputs. 20 (out of 138) different problematic inputs observed in logicsimulations for the revised design are simulated with a transient simulation time of 10 us for each.The simulation results are shown in Figure 22, 23, 24. In addition, 55 random inputs are generated inMATLAB (Appendix 3.2) and simulated (Figure 25, 26).As shown in the transistor level simulation results, no numerical oscillations are observed.31
Page 2: AcknowledgementsI would like to tha
Page 5 and 6: A1.3. XOR Cell ....................
Page 7 and 8: Figure 44. Schematic of DFF gate ..
Page 9 and 10: Figure 2. Schematic of three LSFRs
Page 11 and 12: 2.1. Digital Linear Equation Solver
Page 13 and 14: 2.1.2. Revised DesignIn order to pr
Page 15 and 16: 2.1.3. Final DesignThe timing of th
Page 17 and 18: Figure 7. Schematic of the Final So
Page 19 and 20: After verifying the correct operati
Page 21 and 22: 3.1.2. Revised DesignAs mentioned b
Page 23 and 24: Figure 11. CADENCE Schematic of Rev
Page 25 and 26: Figure 12. CADENCE Schematic of the
Page 27 and 28: 4 Implementation Results4.1. Digita
Page 29: Figure 15. MODELSIM Output waveform
Page 33 and 34: Figure 22. CADENCE Output waveforms
Page 39 and 40: Figure 32. Output waveforms_6 for t
Page 41 and 42: Figure 36. Output waveforms_8 for t
Page 43 and 44: 5 Further Improvements and Comments
Page 45 and 46: 7 References1 - "Encryption" , Data
Page 47 and 48: A1.2. AND CellFigure 40. Schematic
Page 49 and 50: A1.4. DLATCH CellFigure 43. Schemat
Page 51 and 52: A1.6. Input BuffersFigure 45. Schem
Page 53 and 54: A1.7.2. Simulation Setup for the Re
Page 55 and 56: A2 VHDL CodesA2.1.Initial Solver (4
Page 57 and 58: Xout (2)
Page 59 and 60: A2.2.2.GenSolver4_tb.vhdAs mentione
Page 61 and 62: endcountfclose(fid);endelsextxt=[xt
Page 63: if(K==N) %if you cannot find a 1 in

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